T. Karaki-Doy, Haedo Jeong, T. Nakagawa, H. Ohmori, T. Kasai
{"title":"Global planarization technique/CMP by high precision polishing and its characteristics","authors":"T. Karaki-Doy, Haedo Jeong, T. Nakagawa, H. Ohmori, T. Kasai","doi":"10.1109/ISSM.1995.524394","DOIUrl":"https://doi.org/10.1109/ISSM.1995.524394","url":null,"abstract":"In this research we built a prototype of planarization polishing or so-called Chemical and Mechanical Polishing (CMP) using high precision mechanical processing techniques, and thereafter, gained an understanding of basic processing characteristics using model device wafers. As a result, notedly better characteristics such as planarity and uniformity than those obtained to date have been achieved and thus we have gained guidelines so as to implement those characteristics as part of the semiconductor manufacturing equipment.","PeriodicalId":289961,"journal":{"name":"Proceedings of International Symposium on Semiconductor Manufacturing","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-09-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128915992","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Development of the yield enhancement system of a high-volume 8-inch wafer fab","authors":"Ping Wang, M. Chan, R. Goodner, F. Lee, R. Ceton","doi":"10.1109/ISSM.1995.524357","DOIUrl":"https://doi.org/10.1109/ISSM.1995.524357","url":null,"abstract":"This presentation describes the development of a state-of-the-art, proactive yield enhancement system during the startup of Motorola's latest high-volume 8-inch MOS 12 fab. The system has demonstrated rapid defect and failure analysis capability, resulting in fast problem identification and providing yield enhancement engineers with information for continuous yield improvement.","PeriodicalId":289961,"journal":{"name":"Proceedings of International Symposium on Semiconductor Manufacturing","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-09-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134365371","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Hidetoshi Koike, H. Ohtsuka, Fumitomo Matsuoka, Masakazu Kakumu, K. Maeguchi
{"title":"Process simplification in deep submicron CMOS fabrication","authors":"Hidetoshi Koike, H. Ohtsuka, Fumitomo Matsuoka, Masakazu Kakumu, K. Maeguchi","doi":"10.1109/ISSM.1995.524351","DOIUrl":"https://doi.org/10.1109/ISSM.1995.524351","url":null,"abstract":"Process simplification in deep submicron CMOS fabrication is discussed. Process step analysis is carried out for standard 1Poly/1Metal CMOS structure, and consequently, both isolation and gate formation process are extracted as items to simplify the process. A combination of shallow trench isolation and single mask step well/gate doping is proposed for deep submicron CMOS fabrication. This new process can achieve a reduction of 5 mask steps and eliminates both well drive-in annealing and field oxidation without performance deterioration. As a result, 10% process step reduction and 20% manufacturing turn-around-time reduction have been realized in comparison to the standard 1Poly/1Metal CMOS process with LOCOS isolation.","PeriodicalId":289961,"journal":{"name":"Proceedings of International Symposium on Semiconductor Manufacturing","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-09-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122423910","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Role of in-line defect sampling methodology in yield management","authors":"R. Nurani, R. Akella, A. Strojwas, R. Wallace","doi":"10.1109/ISSM.1995.524400","DOIUrl":"https://doi.org/10.1109/ISSM.1995.524400","url":null,"abstract":"This paper presents a comprehensive methodology for yield management based on in-line defect inspection. Using the data from fabs we demonstrate algorithms for computing the sampling plan in terms of the number of lots and wafers per lot to sample at different process steps. In making those computations we take into account in-line defect based yield estimation techniques and simulation based sensitivity selection. The in-line defect data presented in this paper are obtained using KLA 21XX wafer inspection systems from fabs across the world.","PeriodicalId":289961,"journal":{"name":"Proceedings of International Symposium on Semiconductor Manufacturing","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-09-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129790144","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Equipment-based course development and implementation: a teamwork approach","authors":"S. Thornton, M. Karakekes, T. White","doi":"10.1109/ISSM.1995.524367","DOIUrl":"https://doi.org/10.1109/ISSM.1995.524367","url":null,"abstract":"Advanced Micro Device's (AMD) Austin Wafer Fabrication Division is undergoing an organizational transformation. AMD has named this transformation the Journey to Excellence (JTE). The Journey involves multiple initiatives supporting increasingly sophisticated technology and fab processes. AMD takes the view that only through continuous efforts to learn new skills and improve will the company meet the challenges of a fiercely competitive and constantly changing business environment. JTE requires that employees across the organization learn continuously.","PeriodicalId":289961,"journal":{"name":"Proceedings of International Symposium on Semiconductor Manufacturing","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-09-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129890063","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Low cost and flexible data analysis system to find appropriate corrective action for yield deteriorations in LSI manufacturing","authors":"A. Yamanaka, M. Mizuno, R. Ariyoshi, O. Nozawa","doi":"10.1109/ISSM.1995.524369","DOIUrl":"https://doi.org/10.1109/ISSM.1995.524369","url":null,"abstract":"Shortening failure analysis TAT to find appropriate corrective action to resolve low yield problems is one of the most effective methods to improve profitability of LSE manufacturing. We have developed and are successfully using a low cost data analysis system for such purposes. Simple C-shell script programming and AWK programming were used for this development. These tools are so easy to handle that the user of the system, device engineers, were able to construct the system, which made the system friendly and easy to be modified.","PeriodicalId":289961,"journal":{"name":"Proceedings of International Symposium on Semiconductor Manufacturing","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-09-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115145436","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Evaluation for fab performance using CPO","authors":"Y. Ito, H. Ogawa, H. Tani","doi":"10.1109/ISSM.1995.524409","DOIUrl":"https://doi.org/10.1109/ISSM.1995.524409","url":null,"abstract":"Tries to evaluate the investment effect ofthe whole factory by grasping the process cost precisely, classifying its structure, and identifying useless cost factors. As an evaluation index, we defined and used the CPO (Cost of Process Ownership), which is the cost per wafer in each process step based on the configuration of equipment installed in the factory and the configuration of product types manufactured there. This index was developed by making some improvements to the CEO (Cost of Equipment Ownership) model. We will report the definition ofthe CPO we are using and some examples of CPO utilization.","PeriodicalId":289961,"journal":{"name":"Proceedings of International Symposium on Semiconductor Manufacturing","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120946921","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
T. Shihata, K. Ino, N. Konishi, T. Ohmi, C. Urano, H. Enosawa
{"title":"Through-UHV-Pump Impurity Back Diffusion Under Large Gas Flow and Its Minimization","authors":"T. Shihata, K. Ino, N. Konishi, T. Ohmi, C. Urano, H. Enosawa","doi":"10.1109/ISSM.1995.524412","DOIUrl":"https://doi.org/10.1109/ISSM.1995.524412","url":null,"abstract":"","PeriodicalId":289961,"journal":{"name":"Proceedings of International Symposium on Semiconductor Manufacturing","volume":"82 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131806413","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Proceedings of International Symposium on Semiconductor Manufacturing","authors":"","doi":"10.1109/issm.1995.524344","DOIUrl":"https://doi.org/10.1109/issm.1995.524344","url":null,"abstract":"","PeriodicalId":289961,"journal":{"name":"Proceedings of International Symposium on Semiconductor Manufacturing","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134274527","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}