{"title":"Compressed Learning in MCA Architectures to Tolerate Malicious Noise","authors":"B. Paudel, S. Tragoudas","doi":"10.1109/IOLTS56730.2022.9897622","DOIUrl":"https://doi.org/10.1109/IOLTS56730.2022.9897622","url":null,"abstract":"It is shown that compressed learning tolerates adversarial attacks effectively and that classification accuracy is impacted minimally when the compression ratio is selected appropriately. An approach to select the compression ratio is presented. It is also shown that compressed learning is at least as tolerant to adversarial noise as the more power consuming compressive sensing method. Tolerance to adversarial attacks increases when the compressed learning-based neural network architecture is implemented on circuits that use Memristive Crossbar Arrays (MCAs). This paper shows that implementation on an MCA-based analog hardware circuit tolerates adversarial attacks more effectively than a hybrid MCA-based architecture while improving on latency and power consumption.","PeriodicalId":274595,"journal":{"name":"2022 IEEE 28th International Symposium on On-Line Testing and Robust System Design (IOLTS)","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-09-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126829318","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"MLC: A Machine Learning Based Checker For Soft Error Detection In Embedded Processors","authors":"Nooshin Nosrati, M. Jenihhin, Z. Navabi","doi":"10.1109/IOLTS56730.2022.9897309","DOIUrl":"https://doi.org/10.1109/IOLTS56730.2022.9897309","url":null,"abstract":"With deep submicron scaling, the occurrence of soft errors has become a major reliability challenge for electronic systems. This work proposes a Machine Learning-based Checker (MLC) to protect hard-core processors against radiation-induced soft errors. MLC is an independent hardware unit that implements an ML algorithm to detect soft errors in a processor. The work presented here selects input features from key processor signals for creating a dataset for training. The dataset trains an ML model offline for learning the correct behavior of the processor and detecting soft errors at run-time. The inference of this trained ML is implemented in the MLC hardware that runs along with the processor. Several ML models have been considered for the inference phase, and XGBoost implementation has shown to be the best in terms of hardware overhead and accuracy. The proposed scheme is applied to a RISC-V-like processor, called SAYAC, as a case study.","PeriodicalId":274595,"journal":{"name":"2022 IEEE 28th International Symposium on On-Line Testing and Robust System Design (IOLTS)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-09-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128739936","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
G. Kumar, Anjum Riaz, Yamuna Prasad, Satyadev Ahlawat
{"title":"On Attacking IJTAG Architecture based on Locking SIB with Security LFSR","authors":"G. Kumar, Anjum Riaz, Yamuna Prasad, Satyadev Ahlawat","doi":"10.1109/IOLTS56730.2022.9897172","DOIUrl":"https://doi.org/10.1109/IOLTS56730.2022.9897172","url":null,"abstract":"In recent decennium, hardware security has gained a lot of attention due to different types of attacks being launched, such as IP theft, reverse engineering, counterfeiting, etc. The critical testing infrastructure incorporated into ICs is very popular among attackers to mount side-channel attacks. The IEEE standard 1687 (IJTAG) is one such testing infrastructure that is the focus of attackers these days. To secure access to the IJTAG network, various techniques based on Locking SIB (LSIB) have been proposed. One such very effective technique makes use of Security Linear Feedback Shift Register (SLFSR) along with LSIB. The SLFSR obfuscates the scan chain information from the attacker and hence makes the brute-force attack against LSIB ineffective.In this work, it is shown that the SLFSR based Locking SIB is vulnerable to side-channel attacks. A power analysis attack along with known-plaintext attack is used to determine the IJTAG network structure. First, the known-plaintext attack is used to retrieve the SLFSR design information. This information is further used along with power analysis attack to determine the exact length of the scan chain which in turn breaks the whole security scheme. Further, a countermeasure is proposed to prevent the aforementioned hybrid attack.","PeriodicalId":274595,"journal":{"name":"2022 IEEE 28th International Symposium on On-Line Testing and Robust System Design (IOLTS)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-09-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122543416","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Adaptive Block Error Correction for Memristive Crossbars","authors":"Surendra Hemaram, M. Mayahinia, M. Tahoori","doi":"10.1109/IOLTS56730.2022.9897817","DOIUrl":"https://doi.org/10.1109/IOLTS56730.2022.9897817","url":null,"abstract":"Matrix-vector multiplication (MVM) is one of the most frequent operations performed in deep learning and big data applications. On the other hand, the Memory wall problem in traditional processor-centric architectures limits the performance of these applications. The crossbar array of emerging non-volatile memristive devices (memristive crossbar) provides an energy-efficient hardware implementation of MVM for deep learning accelerators and edge computing hardware. However, non-idealities as well as manufacturing and runtime defects of the memristive devices may severely impact the reliability of target applications. This paper presents a new online block error correction technique for memristive crossbars. It enables reliable MVM computation by combining the idea of checksum and Hamming code-based linear coding scheme. The proposed method can correct any number of errors in one particular array block containing multiple columns. An adaptive error correction coding strategy is also presented, so that the ratio of data columns to the parity checksum columns can be adjusted at runtime based on the fault rate, enabling the optimum use of data and parity checksum columns.","PeriodicalId":274595,"journal":{"name":"2022 IEEE 28th International Symposium on On-Line Testing and Robust System Design (IOLTS)","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-09-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126309253","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
G. Gavarini, Diego Stucchi, A. Ruospo, G. Boracchi, Ernesto Sánchez
{"title":"Open-Set Recognition: an Inexpensive Strategy to Increase DNN Reliability","authors":"G. Gavarini, Diego Stucchi, A. Ruospo, G. Boracchi, Ernesto Sánchez","doi":"10.1109/IOLTS56730.2022.9897805","DOIUrl":"https://doi.org/10.1109/IOLTS56730.2022.9897805","url":null,"abstract":"Deep Neural Networks (DNNs) are nowadays widely used in low-cost accelerators, characterized by limited computational resources. These models, and in particular DNNs for image classification, are becoming increasingly popular in safety-critical applications, where they are required to be highly reliable. Unfortunately, increasing DNNs reliability without computational overheads, which might not be affordable in low-power devices, is a non-trivial task. Our intuition is to detect network executions affected by faults as outliers with respect to the distribution of normal network’s output. To this purpose, we propose to exploit Open-Set Recognition (OSR) techniques to perform Fault Detection in an extremely low-cost manner. In particuar, we analyze the Maximum Logit Score (MLS), which is an established Open-Set Recognition technique, and compare it against other well-known OSR methods, namely OpenMax, energy-based outof-distribution detection and ODIN. Our experiments, performed on a ResNet-20 classifier trained on CIFAR-10 and SVHN datasets, demonstrate that MLS guarantees satisfactory detection performance while adding a negligible computational overhead. Most remarkably, MLS is extremely convenient to conFigure and deploy, as it does not require any modification or re-training of the existing network. A discussion of the advantages and limitations of the analysed solutions concludes the paper.","PeriodicalId":274595,"journal":{"name":"2022 IEEE 28th International Symposium on On-Line Testing and Robust System Design (IOLTS)","volume":"50 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-09-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134295229","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A. Portaluri, S. Azimi, C. D. Sio, L. Sterpone, D. M. Codinachs
{"title":"Radiation-induced Effects on DMA Data Transfer in Reconfigurable Devices","authors":"A. Portaluri, S. Azimi, C. D. Sio, L. Sterpone, D. M. Codinachs","doi":"10.1109/IOLTS56730.2022.9897262","DOIUrl":"https://doi.org/10.1109/IOLTS56730.2022.9897262","url":null,"abstract":"As the adoption of SRAM-based FPGAs and Reconfigurable SoCs for High-Performance Computing increased in the last years, the use of Direct Memory Access for data transfer becomes a key feature of many reconfigurable applications even in the space industry. For such kinds of applications, radiation-induced effects are a serious issue that mines the correctness and success of mission-critical tasks. In this paper, we evaluate the effects of proton-induced errors on a DMA-based application implemented on a Xilinx Zynq-7020 FPGA in order to quantify the robustness of this module in a typical hardware-accelerated configuration. The obtained results confirm the high criticality of the DMA module on programmable logic. Moreover, the Multiple Bits Upsets effect has been evaluated. The most recurring patterns have been reported in order to provide further tools to better characterize the behavior of these systems under future fault injection campaigns, as demonstrated in the experimental results.","PeriodicalId":274595,"journal":{"name":"2022 IEEE 28th International Symposium on On-Line Testing and Robust System Design (IOLTS)","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-09-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114484698","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Quantum Noise in the Flow of Time: A Temporal Study of the Noise in Quantum Computers","authors":"Betis Baheri, Qiang Guan, V. Chaudhary, A. Li","doi":"10.1109/IOLTS56730.2022.9897404","DOIUrl":"https://doi.org/10.1109/IOLTS56730.2022.9897404","url":null,"abstract":"Over the last couple of years, Quantum Computing (QC) has captured the interest of computer scientists due to the fact of quantum speedup, the possibility of solving NPhard problems, and achieving higher compute power. However, mitigating the impact of the noise inside each quantum device presents an immediate challenge. These changes open up new opportunities to investigate the effect of calibration parameters for individual characteristics of each qubit in a manner of time. In this paper, we investigate the temporal behavior of noisy intermediate-scale quantum (NISQ) computers based on calibration data and the characteristics of individual devices. In particular, we collect calibration data of IBM-Q machines over the last two years and compare the quantum error robustness against the processor types, quantum topology, and quantum volumes of the IBM-Q machines.","PeriodicalId":274595,"journal":{"name":"2022 IEEE 28th International Symposium on On-Line Testing and Robust System Design (IOLTS)","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-09-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121672255","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"About IOLTS","authors":"","doi":"10.1109/iolts56730.2022.9897676","DOIUrl":"https://doi.org/10.1109/iolts56730.2022.9897676","url":null,"abstract":"","PeriodicalId":274595,"journal":{"name":"2022 IEEE 28th International Symposium on On-Line Testing and Robust System Design (IOLTS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-09-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131154664","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Amalia-Artemis Koufopoulou, Kalliopi Xevgeni, Athanasios Papadimitriou, M. Psarakis, D. Hély
{"title":"Security and Reliability Evaluation of Countermeasures implemented using High-Level Synthesis","authors":"Amalia-Artemis Koufopoulou, Kalliopi Xevgeni, Athanasios Papadimitriou, M. Psarakis, D. Hély","doi":"10.1109/IOLTS56730.2022.9897824","DOIUrl":"https://doi.org/10.1109/IOLTS56730.2022.9897824","url":null,"abstract":"As the complexity of digital circuits increases, High-Level Synthesis (HLS) is becoming a valuable tool to increase productivity and design reuse by utilizing relevant Electronic Design Automation (EDA) flows, either for Application-Specific Integrated Circuits (ASIC) or for Field Programmable Gate Arrays (FPGA). Side Channel Analysis (SCA) and Fault Injection (FI) attacks are powerful hardware attacks, capable of greatly weakening the theoretical security levels of secure implementations. Furthermore, critical applications demand high levels of reliability including fault tolerance. The lack of security and reliability driven optimizations in HLS tools makes it necessary for the HLS-based designs to validate that the properties of the algorithm and the countermeasures have not been compromised due to the HLS flow. In this work, we provide results on the resilience evaluation of HLS-based FPGA implementations for the aforementioned threats. As a test case, we use multiple versions of an on-the-fly SBOX algorithm integrating different countermeasures (hiding and masking), written in C and implemented using Vivado HLS. We perform extensive evaluations for all the designs and their optimization scenarios. The results provide evidence of issues arising from HLS optimizations on the security and reliability of cryptographic implementations. Furthermore, the results put HLS algorithms to the test of designing secure accelerators and can lead to improving them towards the goal of increasing productivity in the domain of secure and reliable cryptographic implementations.","PeriodicalId":274595,"journal":{"name":"2022 IEEE 28th International Symposium on On-Line Testing and Robust System Design (IOLTS)","volume":"380 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-09-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116636581","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A Software Approach Towards Defeating Power Management Side Channel Leakage","authors":"Md. Nazmul Islam, S. Kundu","doi":"10.1109/IOLTS56730.2022.9897191","DOIUrl":"https://doi.org/10.1109/IOLTS56730.2022.9897191","url":null,"abstract":"Hardware Trojans are malicious, undesired, intentional modifications introduced in an Integrated Circuit (IC) which can be leveraged by a knowledgeable adversary to compromise the security of the IC. Trojans might be designed to modify the functionality of an IC, disable the security of a chip, access secret information or even destroy a system. In this paper, we propose PMU-Trojan, a hardware Trojan for leaking confidential information, such as, cryptographic secret key covertly to an adversary. For information leakage by hardware Trojan, we exploit a backdoor created by Power Management Unit (PMU) in Multi Processor System on Chip (MPSoC). PMU is a system block that initiates the voltage and the frequency changes to facilitate flexible power management and energy efficiency. It transmits voltage level change request to power supply. In this paper, we leverage this facility as an information side-channel to leak information to power-supply co-tenants. While the proposed approach can be generalized for any kind of secret information leakage, for the purpose of illustration, in this work, we focus on leaking Advanced Encryption Standard (AES) key. We demonstrate the working principle in Linux environment where a co-tenant thread monitors the change in voltage level and receives side-channel information from a thread affected by PMU-Trojan. The proposed Trojan defeats the traditional Trojan detection and suppression methods due to low information bit rate spread over long duration by a Trojan unit dissipating power at mere pico-Watts level. We propose a novel technique to defeat power management side channel by dynamically tuning processor power limit. The proposed software based solution towards suppressing PMU-Trojan is demonstrated on Intel computing platform using RAPL (Running Average Power Limit) interface.","PeriodicalId":274595,"journal":{"name":"2022 IEEE 28th International Symposium on On-Line Testing and Robust System Design (IOLTS)","volume":"53 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-09-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123801098","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}