{"title":"MLC: A Machine Learning Based Checker For Soft Error Detection In Embedded Processors","authors":"Nooshin Nosrati, M. Jenihhin, Z. Navabi","doi":"10.1109/IOLTS56730.2022.9897309","DOIUrl":null,"url":null,"abstract":"With deep submicron scaling, the occurrence of soft errors has become a major reliability challenge for electronic systems. This work proposes a Machine Learning-based Checker (MLC) to protect hard-core processors against radiation-induced soft errors. MLC is an independent hardware unit that implements an ML algorithm to detect soft errors in a processor. The work presented here selects input features from key processor signals for creating a dataset for training. The dataset trains an ML model offline for learning the correct behavior of the processor and detecting soft errors at run-time. The inference of this trained ML is implemented in the MLC hardware that runs along with the processor. Several ML models have been considered for the inference phase, and XGBoost implementation has shown to be the best in terms of hardware overhead and accuracy. The proposed scheme is applied to a RISC-V-like processor, called SAYAC, as a case study.","PeriodicalId":274595,"journal":{"name":"2022 IEEE 28th International Symposium on On-Line Testing and Robust System Design (IOLTS)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2022-09-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2022 IEEE 28th International Symposium on On-Line Testing and Robust System Design (IOLTS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IOLTS56730.2022.9897309","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 2
Abstract
With deep submicron scaling, the occurrence of soft errors has become a major reliability challenge for electronic systems. This work proposes a Machine Learning-based Checker (MLC) to protect hard-core processors against radiation-induced soft errors. MLC is an independent hardware unit that implements an ML algorithm to detect soft errors in a processor. The work presented here selects input features from key processor signals for creating a dataset for training. The dataset trains an ML model offline for learning the correct behavior of the processor and detecting soft errors at run-time. The inference of this trained ML is implemented in the MLC hardware that runs along with the processor. Several ML models have been considered for the inference phase, and XGBoost implementation has shown to be the best in terms of hardware overhead and accuracy. The proposed scheme is applied to a RISC-V-like processor, called SAYAC, as a case study.