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2007 IEEE International Symposium on Circuits and Systems最新文献

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FPGA Implementation of LDPC Decoders Based on Joint Row-column Decoding Algorithm 基于联合行-列译码算法的LDPC解码器FPGA实现
2007 IEEE International Symposium on Circuits and Systems Pub Date : 2007-05-27 DOI: 10.1109/ISCAS.2007.378837
Zhiyong He, S. Roy, P. Fortier
{"title":"FPGA Implementation of LDPC Decoders Based on Joint Row-column Decoding Algorithm","authors":"Zhiyong He, S. Roy, P. Fortier","doi":"10.1109/ISCAS.2007.378837","DOIUrl":"https://doi.org/10.1109/ISCAS.2007.378837","url":null,"abstract":"This paper presents a joint row-column decoding algorithm for the decoding of low-density parity-check (LDPC) codes. Simulation indicates that the proposed algorithm improves the performance in both the waterfall region and the error floor region. By combining row processing with column processing, the joint row-column decoding algorithm reduces the storage requirements of extrinsic messages and avoids memory conflicts and routing congestion during the exchanges of extrinsic messages. Implementation results into field programmable gate array (FPGA) devices indicate that the proposed algorithm reduces the hardware costs by 30% and increases the decoding speed by a factor of four. A 40-parallel decoder attains a throughput of 2 Gbits/sec by using up to 20 % of the generic logic resources in a Xilinx XC4LX160 device","PeriodicalId":274010,"journal":{"name":"2007 IEEE International Symposium on Circuits and Systems","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126466282","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 15
A Missing Data-based Feature Fusion Strategy for Noise-Robust Automatic Speech Recognition Using Noisy Sensors 基于缺失数据特征融合的噪声传感器语音自动识别策略
2007 IEEE International Symposium on Circuits and Systems Pub Date : 2007-05-27 DOI: 10.1109/ISCAS.2007.378087
C. Demiroğlu, David V. Anderson, M. Clements
{"title":"A Missing Data-based Feature Fusion Strategy for Noise-Robust Automatic Speech Recognition Using Noisy Sensors","authors":"C. Demiroğlu, David V. Anderson, M. Clements","doi":"10.1109/ISCAS.2007.378087","DOIUrl":"https://doi.org/10.1109/ISCAS.2007.378087","url":null,"abstract":"Feature fusion is a popular approach for improving the accuracy of speech recognition systems in noisy environments. Although the feature fusion method performs well for high and moderate SNRs, its performance degrades rapidly at low SNRs. Moreover, auxiliary features that are robust to acoustic noise may sometimes be unreliable, because of sensor misplacements etc, which can further degrade the performance. Furthermore, noisy sensor signals may exist not only in the test data but also in the training data. Here, the feature fusion method is combined with a missing data technique to improve noise-robustness at low SNRs. An auxiliary feature is used both for feature fusion and for detecting the unreliable speech frames. Noisy auxiliary features are addressed using a missing data approach both in the decoding and training systems. In the experiments, substantial improvements in the feature fusion method are obtained especially at low SNRs. The proposed missing data-based training strategy is also shown to improve the accuracy significantly.","PeriodicalId":274010,"journal":{"name":"2007 IEEE International Symposium on Circuits and Systems","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126479898","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
On equalization of channels with ZP precoders 用ZP预编码器实现信道均衡
2007 IEEE International Symposium on Circuits and Systems Pub Date : 2007-05-27 DOI: 10.1109/ISCAS.2007.378417
P. Vaidyanathan
{"title":"On equalization of channels with ZP precoders","authors":"P. Vaidyanathan","doi":"10.1109/ISCAS.2007.378417","DOIUrl":"https://doi.org/10.1109/ISCAS.2007.378417","url":null,"abstract":"In communication systems which used filter bank precoders with zero padding (ZP) at the transmitter, the effect of an FIR channel can be equalized without the use of IIR equalizers. In this paper a number of observations are made with regard to the noise gain created by the equalizer at the receiver. If the number of received samples per block actually utilized in equalization is reduced to the number of transmitted samples per block, then the noise gain can be very large for channels with zeros outside the unit circle. As the number of utilized received samples increases the situation improves. Most importantly, it is shown that when all the redundant samples in each block are utilized for estimation of transmitted symbols then the noise gain is not sensitive to whether the channel zeros are inside, on, or outside the unit circle, and depends only on the FIR channel autocorrelation","PeriodicalId":274010,"journal":{"name":"2007 IEEE International Symposium on Circuits and Systems","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126543797","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
A VLSI Architecture for a Fast Computation of the 2-D Discrete Wavelet Transform 一种快速计算二维离散小波变换的VLSI结构
2007 IEEE International Symposium on Circuits and Systems Pub Date : 2007-05-27 DOI: 10.1109/ISCAS.2007.378672
Yu Hu, Qing Li, Siwei Ma, C.-C. Jay Kuo
{"title":"A VLSI Architecture for a Fast Computation of the 2-D Discrete Wavelet Transform","authors":"Yu Hu, Qing Li, Siwei Ma, C.-C. Jay Kuo","doi":"10.1109/ISCAS.2007.378672","DOIUrl":"https://doi.org/10.1109/ISCAS.2007.378672","url":null,"abstract":"Video encoding to yield a decoder-friendly H.264 bit stream that consumes less decoding power yet with little coding efficiency degradation is investigated in this work. The in pipeline mode enhances the computing time by deblocking filters (ADF). We first propose a power among the three stages and by incorporating parallelism at encoder performs the rate-distortion-decoder complexity optimization (RDC) to save the decoder power needed for deblocking filter operations, which is called the decoder-friendly adaptive deblocking filter (DF-ADF) mode decision. The RDC optimization framework presents a way to balance coding efficiency and the ADF decoding cost in the mode decision process. The effectiveness of the proposed DF-ADF algorithm is demonstrated by experiments with diverse video contents and bit rates.","PeriodicalId":274010,"journal":{"name":"2007 IEEE International Symposium on Circuits and Systems","volume":"187 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128171178","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Probabilistic Modelling of Phase-tuned Disparity Energy Neuron Populations 相位调谐视差能量神经元种群的概率建模
2007 IEEE International Symposium on Circuits and Systems Pub Date : 2007-05-27 DOI: 10.1109/ISCAS.2007.377862
Eric K. C. Tsang, Bertram E. Shi
{"title":"Probabilistic Modelling of Phase-tuned Disparity Energy Neuron Populations","authors":"Eric K. C. Tsang, Bertram E. Shi","doi":"10.1109/ISCAS.2007.377862","DOIUrl":"https://doi.org/10.1109/ISCAS.2007.377862","url":null,"abstract":"We present a low dimensional Bayes probabilistic model for the population of binocular disparity energy neurons centered at the same retinal location, but selective to different disparities by phase shifts between the left and right monocular receptive fields. The model accurately predicts response distributions of simulated binocular disparity energy neurons. It provides a probabilistic explanation for the decrease in the reliability of the population responses for large disparities. Applied to vergence control, it generates more reliable responses than using the preferred disparity of the most responsive neuron as the control signal.","PeriodicalId":274010,"journal":{"name":"2007 IEEE International Symposium on Circuits and Systems","volume":"71 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125980894","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A 3.8-Gb/s CMOS Laser Driver with Automatic Power Control Using Thermistors 采用热敏电阻自动控制功率的3.8 gb /s CMOS激光驱动器
2007 IEEE International Symposium on Circuits and Systems Pub Date : 2007-05-27 DOI: 10.1109/ISCAS.2007.377834
Day-Uei Li, Wen-Hui Chen, Long-Xi Chang, Chueh-Hao Yu
{"title":"A 3.8-Gb/s CMOS Laser Driver with Automatic Power Control Using Thermistors","authors":"Day-Uei Li, Wen-Hui Chen, Long-Xi Chang, Chueh-Hao Yu","doi":"10.1109/ISCAS.2007.377834","DOIUrl":"https://doi.org/10.1109/ISCAS.2007.377834","url":null,"abstract":"A 3.8-Gb/s laser driver with automatic power control (APC) using thermistors is presented. The chip was fabricated in 0.25mum 1P5M CMOS process. With a waveform shaping circuit, the driver could generate a 5mA to 60mA modulation current with its duty cycle maintained at 50%. A modified MUX circuit is also introduced to improve the jitter performance of both the direct and latched data output. And with a thermistor-APC compensation circuit, the laser power could be maintained within a temperature range from -30 degC to 80degC without using any monitor photodiode. Measurements on mounted chips show clear electrical eye diagrams operating over 3.8-Gb/s data rate with typical rise/fall times (20% to 80%) of 104/109ps. Moreover, an optical eye diagram is also demonstrated by connecting the driver with a 2.5-Gb/s 1310nm laser diode.","PeriodicalId":274010,"journal":{"name":"2007 IEEE International Symposium on Circuits and Systems","volume":"54 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121681404","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Highly Linear V/I Converter with Programmable Current Mirrors 具有可编程电流镜的高线性V/I转换器
2007 IEEE International Symposium on Circuits and Systems Pub Date : 2007-05-27 DOI: 10.1109/ISCAS.2007.378081
I. Padilla, J. Ramírez-Angulo, R. Carvajal, A. López-Martín
{"title":"Highly Linear V/I Converter with Programmable Current Mirrors","authors":"I. Padilla, J. Ramírez-Angulo, R. Carvajal, A. López-Martín","doi":"10.1109/ISCAS.2007.378081","DOIUrl":"https://doi.org/10.1109/ISCAS.2007.378081","url":null,"abstract":"A highly linear voltage-to-current (V/I) converter is presented. A variant of the FVF denoted \"flipped folded voltage follower\" (FFVF) and a useful application in a voltage-to-current (V/I) converter are presented. A modification using floating gates to provide gain programmability is discussed. Simulation and experimental results of fabricated test chip show the high linearity of the scheme","PeriodicalId":274010,"journal":{"name":"2007 IEEE International Symposium on Circuits and Systems","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121778065","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 21
Crosstalk-Aware Transmitter Pulse-Shaping for Parallel Chip-to-Chip Links 并行芯片到芯片链路的串扰感知发射机脉冲整形
2007 IEEE International Symposium on Circuits and Systems Pub Date : 2007-05-27 DOI: 10.1109/ISCAS.2007.378308
M. Bichan, A. C. Carusone
{"title":"Crosstalk-Aware Transmitter Pulse-Shaping for Parallel Chip-to-Chip Links","authors":"M. Bichan, A. C. Carusone","doi":"10.1109/ISCAS.2007.378308","DOIUrl":"https://doi.org/10.1109/ISCAS.2007.378308","url":null,"abstract":"Crosstalk and inter-symbol interference are major obstacles towards increasing the data rate of chip-to-chip links. They are especially important in long, single-ended, parallel links. We find that when crosstalk is the dominant source of received noise, a transmitted pulse shape that combines slew-rate limiting with transmitter pre-emphasis is preferred. We present a framework for choosing a transmit pulse-shape that minimizes the combined effects of both crosstalk and inter-symbol interference. When implementing this optimal pulse shape, filter taps that are fractionally spaced are beneficial. As a test, various pulse shapes were injected into a test channel with three parallel microstrip lines, and the received eye diagrams were measured. The crosstalk-aware pulse shape results in an increased eye opening when compared to square and pre-emphasis pulses","PeriodicalId":274010,"journal":{"name":"2007 IEEE International Symposium on Circuits and Systems","volume":"326 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115873068","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A CMOS Low Power Fully Digital Adaptive Power Delivery System Based on Finite State Machine Control 基于有限状态机控制的CMOS低功耗全数字自适应送电系统
2007 IEEE International Symposium on Circuits and Systems Pub Date : 2007-05-27 DOI: 10.1109/ISCAS.2007.378253
Yong-Bin Kim, Kyung Ki Kim, J. Doyle
{"title":"A CMOS Low Power Fully Digital Adaptive Power Delivery System Based on Finite State Machine Control","authors":"Yong-Bin Kim, Kyung Ki Kim, J. Doyle","doi":"10.1109/ISCAS.2007.378253","DOIUrl":"https://doi.org/10.1109/ISCAS.2007.378253","url":null,"abstract":"A fully digital self-adjusting high efficiency power supply system has been developed based on an FSM control scheme. The system dynamically monitors circuit performance with a slacktime detector, and provides a substantially constant minimum-supply voltage for digital processors to properly operate at a given frequency with regard to different process-voltage-temperature (PVT) and load conditions. The digital FSM scheme significantly reduces the complexity of control loop implementation (<1800 gates) and its own power consumption (<100muW)","PeriodicalId":274010,"journal":{"name":"2007 IEEE International Symposium on Circuits and Systems","volume":"28 6","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"113938420","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A Low Power 4-bit Interleaved Burst Sampling ADC for Sub-GHz Impulse UWB Radio 一种用于次ghz脉冲UWB无线电的低功耗4位交错突发采样ADC
2007 IEEE International Symposium on Circuits and Systems Pub Date : 2007-05-27 DOI: 10.1109/ISCAS.2007.378257
Xiaodong Zhang, M. Bayoumi
{"title":"A Low Power 4-bit Interleaved Burst Sampling ADC for Sub-GHz Impulse UWB Radio","authors":"Xiaodong Zhang, M. Bayoumi","doi":"10.1109/ISCAS.2007.378257","DOIUrl":"https://doi.org/10.1109/ISCAS.2007.378257","url":null,"abstract":"This paper presents a low power 4-bit ADC for sub-GHz ultra wideband (UWB) receivers. The power efficiency is achieved by taking advantage of the low duty cycle feature of UWB impulse. After the synchronization is achieved, the burst-mode sampling approach is employed to avoid unnecessary operations. So, the ADC only samples at the time when a pulse is expected and stays in standby during the rest of the time. The proposed burst sampling ADC employs five interleaved pipeline flash ADCs controlled by a low duty cycle 25 MHz sampling clock with five different phases. The resistor ladder reference circuit is eliminated by using a modified quantum voltage comparator, which can generate the reference voltages internally. The proposed ADC has been designed and simulated by using TSMC 0.0mum CMOS process. Simulation results show that the proposed 4-bit ADC can operate at 1G sample/s for UWB impulse with power consumption of 7.6 mW.","PeriodicalId":274010,"journal":{"name":"2007 IEEE International Symposium on Circuits and Systems","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131360420","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
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