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2007 IEEE International Symposium on Circuits and Systems最新文献

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On Problems of Compensated Continuous-Time Chebyshev Filters in the Time Domain 时域补偿连续切比雪夫滤波器的若干问题
2007 IEEE International Symposium on Circuits and Systems Pub Date : 2007-05-27 DOI: 10.1109/ISCAS.2007.378725
J. Piskorowski
{"title":"On Problems of Compensated Continuous-Time Chebyshev Filters in the Time Domain","authors":"J. Piskorowski","doi":"10.1109/ISCAS.2007.378725","DOIUrl":"https://doi.org/10.1109/ISCAS.2007.378725","url":null,"abstract":"Continuous-time filters often require a compensation, because some of them are characterized by considerable distortions in the group delay response. However, a process of the group delay compensation always causes an extension of the transient state of the compensated filter. This problem is often omitted in the literature, and hence is the main scope of this work. In this paper, we propose a new theoretical method for shortening the transients in phase-compensated continuous-time filters. Using the compensated low-pass Chebyshev filter, we introduce time-varying parameters to its structure for the purpose of the minimization of the transient state. Results verifying the effectiveness of the proposed approach are presented and compared to the traditional filters.","PeriodicalId":274010,"journal":{"name":"2007 IEEE International Symposium on Circuits and Systems","volume":"91 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123626776","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
A 1.9mW Portable ADPLL-based Frequency Synthesizer for High Speed Clock Generation 一种用于高速时钟产生的1.9mW便携式adpll频率合成器
2007 IEEE International Symposium on Circuits and Systems Pub Date : 2007-05-27 DOI: 10.1109/ISCAS.2007.378250
Ming-Hung Chang, Zongxian Yang, W. Hwang
{"title":"A 1.9mW Portable ADPLL-based Frequency Synthesizer for High Speed Clock Generation","authors":"Ming-Hung Chang, Zongxian Yang, W. Hwang","doi":"10.1109/ISCAS.2007.378250","DOIUrl":"https://doi.org/10.1109/ISCAS.2007.378250","url":null,"abstract":"An ADPLL-based frequency synthesizer has been designed and implemented with TSMC 130nm technology model. The cores of it are digital controlled oscillator (DCO) and phase frequency detector (PFD). A modified digitally controlled delay element (DCDE) with characteristics of its monotonicity and insensitivity to PVT variations is presented for the DCO design. A new PFD architecture that can finish phase and frequency comparison and adjustment in one reference cycle is presented. This frequency synthesizer can operate from 300MHz to 1GHz, and achieve frequency acquisition in fifteen reference clock cycles (worst case scenario). The peak-to-peak jitter of the output clock is less than 120ps at 300MHz. Furthermore, the design has been ported to TSMC 100nm process as a reusable IP block verification. The total power dissipation of the ADPLL-based frequency synthesizer is 1.9mW (TSMC 100nm technology) at 1GHz with a 1.2V power supply. With such specifications, it is suitable for high speed clock generation in system-on-a-chip (SoC) applications","PeriodicalId":274010,"journal":{"name":"2007 IEEE International Symposium on Circuits and Systems","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123683196","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Modeling Synaptic Plasticity within Networks of Highly Accelerated I&F Neurons 高加速I&F神经元网络中的突触可塑性建模
2007 IEEE International Symposium on Circuits and Systems Pub Date : 2007-05-27 DOI: 10.1109/ISCAS.2007.378289
J. Schemmel, Daniel Brüderle, K. Meier, B. Ostendorf
{"title":"Modeling Synaptic Plasticity within Networks of Highly Accelerated I&F Neurons","authors":"J. Schemmel, Daniel Brüderle, K. Meier, B. Ostendorf","doi":"10.1109/ISCAS.2007.378289","DOIUrl":"https://doi.org/10.1109/ISCAS.2007.378289","url":null,"abstract":"When studying the different aspects of synaptic plasticity, the timescales involved range from milliseconds to hours, thus covering at least seven orders of magnitude. To make this temporal dynamic range accessible to the experimentalist, we have developed a highly accelerated analog VLSI model of leaky integrate and fire neurons. It incorporates fast and slow synaptic facilitation and depression mechanisms in its conductance based synapses. By using a 180 nm process 105 synapses fit on a 25 mm2 die. A single chip can model the temporal evolution of the synaptic weights in networks of up to 384 neurons with an acceleration factor of 105 while recording the neural action potentials with a temporal resolution better than 30 mus biological time. This reduces the time needed for a 10 minute experiment to merely 6 ms, paving the way for complex parameter searches to reproduce biological findings. Due to a digital communication structure larger networks can be built from multiple chips while retaining an acceleration factor of a least 104.","PeriodicalId":274010,"journal":{"name":"2007 IEEE International Symposium on Circuits and Systems","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121164022","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 112
Use of a Variable Wordlength Technique in an OFDM Receiver to Reduce Energy Dissipation 在OFDM接收机中使用变字长技术以减少能量损耗
2007 IEEE International Symposium on Circuits and Systems Pub Date : 2007-05-27 DOI: 10.1109/ISCAS.2007.378105
S. Yoshizawa, Y. Miyanaga
{"title":"Use of a Variable Wordlength Technique in an OFDM Receiver to Reduce Energy Dissipation","authors":"S. Yoshizawa, Y. Miyanaga","doi":"10.1109/ISCAS.2007.378105","DOIUrl":"https://doi.org/10.1109/ISCAS.2007.378105","url":null,"abstract":"Wordlength determination is an indispensable task in digital hardware implementations of signal processing algorithms because the wordlength affects power consumption and system performance. Actual digital systems add extra bits in circuit design to avoid the worst condition caused by lack of dynamic range. However, they still have room to reduce a wordlength during better conditions. We present a variable wordlength technique for dynamically controlling the wordlength used in wireless OFDM receivers. The key point is that the receiver optimizes the wordlength while operating by sensing current receiver performance. The proposed technique can reduce a wordlength compared with use of a fixed wordlength and satisfy the user-required communication quality of PER. The results show that the receiver has reduced dissipated energy by 18.1 to 30.3% with the PER criterion of 10-2.","PeriodicalId":274010,"journal":{"name":"2007 IEEE International Symposium on Circuits and Systems","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121218794","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 14
Automatic Detection of Solder Joint Defects on Integrated Circuits 集成电路焊点缺陷的自动检测
2007 IEEE International Symposium on Circuits and Systems Pub Date : 2007-05-27 DOI: 10.1109/ISCAS.2007.378143
G. Acciani, G. Brunetti, G. Fornarelli
{"title":"Automatic Detection of Solder Joint Defects on Integrated Circuits","authors":"G. Acciani, G. Brunetti, G. Fornarelli","doi":"10.1109/ISCAS.2007.378143","DOIUrl":"https://doi.org/10.1109/ISCAS.2007.378143","url":null,"abstract":"In this paper an automatic inspection method for the diagnosis of solder joint defects on integrated circuits mounted in surface mounting technology is presented. The diagnosis is handled as a classification problem with a neural network approach. Two classes of solder joints have been fixed with respect to the amount of the soldering paste. These correspond to acceptable and non acceptable solder joints to assure the correct working of the integrated circuits. The images of the boards under test are acquired by an acquisition system; then they are pre-processed to extract the region of interest for the diagnosis. A \"geometric\" features vector is extracted from this region and it feeds a multi layer perceptron neural network. Experimental results show that these networks perform high recognition rate and the robustness of the proposed method.","PeriodicalId":274010,"journal":{"name":"2007 IEEE International Symposium on Circuits and Systems","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114317414","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 15
Application of Fast DC Analysis to Partitioning Hypergraphs 快速DC分析在超图划分中的应用
2007 IEEE International Symposium on Circuits and Systems Pub Date : 2007-05-27 DOI: 10.1109/ISCAS.2007.378299
G. Trivedi, H. Narayanan
{"title":"Application of Fast DC Analysis to Partitioning Hypergraphs","authors":"G. Trivedi, H. Narayanan","doi":"10.1109/ISCAS.2007.378299","DOIUrl":"https://doi.org/10.1109/ISCAS.2007.378299","url":null,"abstract":"Partitioning is an important technique for solving graph based problems. The quality of partitions produced by standard methods, for example Fiduccia and Mattheyses (FM) algorithm, depends on the initial random seed partition. In order to get the best partitions, we have to run the partitioner many times with different seed partitions. In this paper, we present a heuristic for producing good seed partitions for partitioning graphs and hypergraphs by analyzing an appropriately derived resistor, current source electrical network and sorting the nodes according to their potentials. This is feasible because we use a special purpose DC analyzer which is very fast and can handle circuits of size up to a million nodes. Experiments have been performed on IBM benchmark hypergraphs on a Pentium-4 machine having 1GB RAM. For larger size hypergraphs, our method outperforms the standard random seed based FM algorithm both in terms of the partitioning time and in terms of the cut-cost.","PeriodicalId":274010,"journal":{"name":"2007 IEEE International Symposium on Circuits and Systems","volume":"63 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114319815","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Collaborative Routing Architecture for FPGA FPGA协同路由架构
2007 IEEE International Symposium on Circuits and Systems Pub Date : 2007-05-27 DOI: 10.1109/ISCAS.2007.378646
Yaling Ma, Mingjie Lin
{"title":"Collaborative Routing Architecture for FPGA","authors":"Yaling Ma, Mingjie Lin","doi":"10.1109/ISCAS.2007.378646","DOIUrl":"https://doi.org/10.1109/ISCAS.2007.378646","url":null,"abstract":"In this paper we present the collaborative routing architecture (CRA), a routing architecture specially designed to achieve high efficiency in hardware and competitive delay performance for a FPGA. This is done by enabling routing resource sharing between different types: (1) long interconnects can be constructed with short bypass interconnects without sacrificing delay performance. (2) switch boxes and connection boxes both are embedded in the switching core of the routing modules. Therefore routing resources such as MUXs can be shared between them on a per-mapping basis. (3) the switching core in CRA can dynamically extend its switching capability, whereas in a conventional switch box, switch matrix is predetermined and therefore static. These architectural features demonstrate significant performance improvements. Using the same logic placement, the CRA yields about 25% reduction in the minimum routing channel width, 20% improvement in overall delay performance for 20 largest MCNC benchmark circuits, when compared with a Virtex-II style baseline FPGA.","PeriodicalId":274010,"journal":{"name":"2007 IEEE International Symposium on Circuits and Systems","volume":"105 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116210949","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Nonlinear, Transient Simulation of Distributed RF Circuits using Discrete-Time Convolution 离散时间卷积的分布式射频电路非线性瞬态仿真
2007 IEEE International Symposium on Circuits and Systems Pub Date : 2007-05-27 DOI: 10.1109/ISCAS.2007.378681
T. Brazil
{"title":"Nonlinear, Transient Simulation of Distributed RF Circuits using Discrete-Time Convolution","authors":"T. Brazil","doi":"10.1109/ISCAS.2007.378681","DOIUrl":"https://doi.org/10.1109/ISCAS.2007.378681","url":null,"abstract":"High frequency circuit simulation involving nonlinear active devices presents special simulation challenges because of the complex distributed linear environments involved, and the increasing need to accommodate wide-spectrum digitally-modulated signal formats operating over very large bandwidths. This contribution describes a simulation approach that is based on discrete-time convolution which allows both transient and steady-state solutions to be obtained with high accuracy, generality and robustness. Examples are given of the application of this kind of simulation to severely nonlinear operation of a high frequency power amplifier employing lumped elements with lossy, dispersive transmission lines. The approach described is also of interest for signal integrity simulations in high speed digital systems.","PeriodicalId":274010,"journal":{"name":"2007 IEEE International Symposium on Circuits and Systems","volume":"62 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116359600","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 13
Galileo L1 Civil Receiver Tracking Loops' Architecture 伽利略L1民用接收机跟踪环路结构
2007 IEEE International Symposium on Circuits and Systems Pub Date : 2007-05-27 DOI: 10.1109/ISCAS.2007.377930
O. Julien, G. Lachapelle, M. Cannon
{"title":"Galileo L1 Civil Receiver Tracking Loops' Architecture","authors":"O. Julien, G. Lachapelle, M. Cannon","doi":"10.1109/ISCAS.2007.377930","DOIUrl":"https://doi.org/10.1109/ISCAS.2007.377930","url":null,"abstract":"This paper introduces the main modulation improvements brought by the future global navigation satellite systems (GNSSs) compared to the currently available GPS C/A signal. Its impact on the code and phase tracking performance is illustrated and its implication on the design of these two tracking loop design is analyzed.","PeriodicalId":274010,"journal":{"name":"2007 IEEE International Symposium on Circuits and Systems","volume":"67 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126308595","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
A Class of Cosine-Modulated Filter Banks with Multiple Prototype Filters 一类具有多原型滤波器的余弦调制滤波器组
2007 IEEE International Symposium on Circuits and Systems Pub Date : 2007-05-27 DOI: 10.1109/ISCAS.2007.378804
Chao Wu, Weiping Zhu, M. Swamy
{"title":"A Class of Cosine-Modulated Filter Banks with Multiple Prototype Filters","authors":"Chao Wu, Weiping Zhu, M. Swamy","doi":"10.1109/ISCAS.2007.378804","DOIUrl":"https://doi.org/10.1109/ISCAS.2007.378804","url":null,"abstract":"In this paper, several new cosine-modulated filter banks (CMFBs) are developed by using multiple prototype filters in conjunction with a proper modulation scheme. First, the conventional CMFB is formulated as a cascade of a modulation matrix and a polyphase matrix with a bidiagonal structure. Under this framework, it is then revealed that the proposed new CMFBs are a special class of paraunitary filter banks (PUFBs), whose polyphase matrices are of different sparse patterns. It is shown that when M prototype filters are used, a full polyphase matrix representing a general PUFB can be obtained, thus providing a bridge connecting CMFBs and PUFBs. It is also shown that with more free parameters involved in the CMFBs, one can achieve a tradeoff between the performance of the filter bank and its design/implementation complexity","PeriodicalId":274010,"journal":{"name":"2007 IEEE International Symposium on Circuits and Systems","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126341478","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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