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2007 IEEE International Symposium on Circuits and Systems最新文献

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A Scalable Load Balanced Birkhoff-von Neumann Symmetric TDM Switch IC for High-Speed Networking Applications 用于高速网络应用的可扩展负载平衡Birkhoff-von Neumann对称TDM开关IC
2007 IEEE International Symposium on Circuits and Systems Pub Date : 2007-05-27 DOI: 10.1109/iscas.2007.378623
C. Chiu, Y. Hsu, M. Kao, Hou-Cheng Tzeng, Ming-Chang Du, Ping-Ling Yang, Ming-Hao Lu, Fanta Chen, Hung-Yu Lin, Jen-Ming Wu, Shuo-Hung Hsu, Yarsun Hsu
{"title":"A Scalable Load Balanced Birkhoff-von Neumann Symmetric TDM Switch IC for High-Speed Networking Applications","authors":"C. Chiu, Y. Hsu, M. Kao, Hou-Cheng Tzeng, Ming-Chang Du, Ping-Ling Yang, Ming-Hao Lu, Fanta Chen, Hung-Yu Lin, Jen-Ming Wu, Shuo-Hung Hsu, Yarsun Hsu","doi":"10.1109/iscas.2007.378623","DOIUrl":"https://doi.org/10.1109/iscas.2007.378623","url":null,"abstract":"For the first time, a scalable load balanced Birkhoff-von Neumann TDM switch IC with SERDES interface circuits for high speed networking applications was implemented. Any NtimesN Birkhoff-von Neumann TDM switch could be constructed recursively from the designed TDM switch IC to achieve switching capacity of hundred gigabits per second or higher. The TDM switch IC contained a digital 8times8 TDM switch core with 8B10B codecs and analog SERDES I/O interfaces. In the I/O interfaces, eight 2.56/3.2Gbps dual-mode 16/20:1 SERDES with CML buffers were developed. The 16/20:1 instead of 8/10:1 serializer and deserializer were used to reduce the required operating frequency in the switch core by half. New half-rate architectures and all static CMOS gates were used in the 16/20:1 serializer and deserializer for the low power consumption. A wide-band CML I/O buffer with our patented PMOS active load scheme was developed. All the implementations were based on the 0.18 mum CMOS technology. Test results showed a 20 Gbps switching capacity for the 8times8 TDM switch IC.","PeriodicalId":274010,"journal":{"name":"2007 IEEE International Symposium on Circuits and Systems","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130628460","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Design and Synthesis of a Three Input Flagged Prefix Adder 三输入标记前缀加法器的设计与合成
2007 IEEE International Symposium on Circuits and Systems Pub Date : 2007-05-27 DOI: 10.1109/ISCAS.2007.378197
V. Dave, E. Oruklu, J. Saniie
{"title":"Design and Synthesis of a Three Input Flagged Prefix Adder","authors":"V. Dave, E. Oruklu, J. Saniie","doi":"10.1109/ISCAS.2007.378197","DOIUrl":"https://doi.org/10.1109/ISCAS.2007.378197","url":null,"abstract":"For multi-operand addition, several techniques, such as carry-save adders, Wallace, and Dadda structures based on counters and compressors have been proposed. This paper proposes a technique to accomplish three-operand addition utilizing regular adder structures such as parallel-prefix adders. One of the advantages of this technique is the elimination of dedicated adder units to perform three-input addition. Conventional prefix adders are modified to generate intermediate outputs called flag bits to allow the addition of a third arbitrary number, thereby accomplishing multi-operand addition. This adder can find its use in applications such as multiplication or multi-media units. An evaluation has been performed for 16-bit three-input flagged prefix adder architectures (TIFPA) in terms of area, delay and power. The performance of this adder design has been compared to that of carry save adders to understand the performance gain of the proposed technique.","PeriodicalId":274010,"journal":{"name":"2007 IEEE International Symposium on Circuits and Systems","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130658005","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
An Online Procedure for Linear-Phase 2-D FIR Filters of Smallest Size with Magnitude Error Constraint 具有幅度误差约束的最小尺寸线性相位2-D FIR滤波器的在线程序
2007 IEEE International Symposium on Circuits and Systems Pub Date : 2007-05-27 DOI: 10.1109/ISCAS.2007.377970
Xiaoping Lai, H. Kwan
{"title":"An Online Procedure for Linear-Phase 2-D FIR Filters of Smallest Size with Magnitude Error Constraint","authors":"Xiaoping Lai, H. Kwan","doi":"10.1109/ISCAS.2007.377970","DOIUrl":"https://doi.org/10.1109/ISCAS.2007.377970","url":null,"abstract":"This paper presents an online procedure that produces the smallest feasible size of two-dimensional (2-D) FIR filters with prescribed magnitude error constraint. The procedure uses the mean square normalized error of constrained and unconstrained least-square filters to produce the initial and the subsequent sizes that converge to the smallest feasible one in a few iterations, where the constrained least-square filters are defined as the least-square filters satisfying the magnitude error constraint. The procedure finally returns a smallest size filter that satisfies the magnitude error constraint and has least total squared magnitude error. Design examples of diamond-shaped, rectangular, and elliptic filters are provided, and comparisons with an exhaustive search are given.","PeriodicalId":274010,"journal":{"name":"2007 IEEE International Symposium on Circuits and Systems","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130671649","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A 32-point FFT based Noise Reduction Algorithm for Single Channel Speech Signals 基于32点FFT的单通道语音信号降噪算法
2007 IEEE International Symposium on Circuits and Systems Pub Date : 2007-05-27 DOI: 10.1109/ISCAS.2007.378659
Kunal Mukherjee, B. Gwee
{"title":"A 32-point FFT based Noise Reduction Algorithm for Single Channel Speech Signals","authors":"Kunal Mukherjee, B. Gwee","doi":"10.1109/ISCAS.2007.378659","DOIUrl":"https://doi.org/10.1109/ISCAS.2007.378659","url":null,"abstract":"In this paper we propose a noise reduction system for single channel speech signals. The system comprises of a 32-point FFT based spectral subtraction method, a variable least mean squares (LMS) filter and a 3-state voice activity detector. The LMS filter is designed to remove musical noise generated during spectral subtraction. It takes the original signal and the result of spectral subtraction as its inputs, and exploits the statistical differences between musical noise and speech to give a natural sounding output. The voice activity detector updates the noise spectrum estimate for spectral subtraction and controls the LMS filter parameters to make it adapt better to the incoming signal. Test cases involving three different non-stationary noise environments resulted in an average improvement of 6dB in the SNR after processing with low musical noise.","PeriodicalId":274010,"journal":{"name":"2007 IEEE International Symposium on Circuits and Systems","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123844755","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
An Approach to Detect Negative Bias Temperature Instability (NBTI) in Ultra-Deep Submicron Technologies 超深亚微米技术中负偏置温度不稳定性(NBTI)的检测方法
2007 IEEE International Symposium on Circuits and Systems Pub Date : 2007-05-27 DOI: 10.1109/ISCAS.2007.378339
R. Carlsten, J. Ralston-Good, D. Goodman
{"title":"An Approach to Detect Negative Bias Temperature Instability (NBTI) in Ultra-Deep Submicron Technologies","authors":"R. Carlsten, J. Ralston-Good, D. Goodman","doi":"10.1109/ISCAS.2007.378339","DOIUrl":"https://doi.org/10.1109/ISCAS.2007.378339","url":null,"abstract":"Negative bias temperature instability (NBTI) is a pMOSFET's degradation mechanism that can result in threshold voltage shift. This shift, if large enough, can cause serious reliability concerns for MOSFET analog and digital circuits. This paper presents a prognostic circuit that measures the VT shift in a pMOSFET and reports its state-of-health.","PeriodicalId":274010,"journal":{"name":"2007 IEEE International Symposium on Circuits and Systems","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123846636","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
Risk Management - beyond Risk Analysis 风险管理-超越风险分析
2007 IEEE International Symposium on Circuits and Systems Pub Date : 2007-05-27 DOI: 10.1109/ISCAS.2007.378614
L. Pinto, R. Maia, L. Tsunechiro, J. Szczupak, B. Dias
{"title":"Risk Management - beyond Risk Analysis","authors":"L. Pinto, R. Maia, L. Tsunechiro, J. Szczupak, B. Dias","doi":"10.1109/ISCAS.2007.378614","DOIUrl":"https://doi.org/10.1109/ISCAS.2007.378614","url":null,"abstract":"Most portfolio models target the risk analysis problem - that is, optimize a set of products or contracts and evaluate the risk associated to the optimum solution. This paper proposes a novel concept for the optimum portfolio problem: evaluate the optimum solution associated to a desired risk level n other words, risks levels are here taken as constraints to be obeyed, not consequences of a decision. The resulting non-linear, integer problem is solved by an efficient framework, based on the real-options concept, minimizing costs and maximizing flexibility. A case study with a real contract portfolio (ranging from months to several years ahead) illustrates the model potential.","PeriodicalId":274010,"journal":{"name":"2007 IEEE International Symposium on Circuits and Systems","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123958534","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
CMOS SOCs at 100 GHz: System Architectures, Device Characterization, and IC Design Examples 100 GHz的CMOS soc:系统架构，器件特性和IC设计示例
2007 IEEE International Symposium on Circuits and Systems Pub Date : 2007-05-27 DOI: 10.1109/ISCAS.2007.378422
S. Voinigescu, S. Nicolson, M. Khanpour, K. W. Tang, K. Yau, N. Seyedfathi, A. Timonov, A. Nachman, G. Eleftheriades, P. Schvan, Ming-Ta Yang
{"title":"CMOS SOCs at 100 GHz: System Architectures, Device Characterization, and IC Design Examples","authors":"S. Voinigescu, S. Nicolson, M. Khanpour, K. W. Tang, K. Yau, N. Seyedfathi, A. Timonov, A. Nachman, G. Eleftheriades, P. Schvan, Ming-Ta Yang","doi":"10.1109/ISCAS.2007.378422","DOIUrl":"https://doi.org/10.1109/ISCAS.2007.378422","url":null,"abstract":"This paper investigates the suitability of 90nm and 65nm GP and LP CMOS technology for SOC applications in the 60GHz to 100GHz range. Examples of system architectures and transceiver building blocks are provided which emphasize the need for aggressively scaled GP CMOS and low-VT transistors if CMOS is to compete with SiGe BiCMOS above 60 GHz. This requirement is in conflict with the 2005-ITRS proposal to use LP CMOS for RF applications.","PeriodicalId":274010,"journal":{"name":"2007 IEEE International Symposium on Circuits and Systems","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123959926","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 36
Triangle-Level Depth Filter Method for Bandwidth Reduction in 3D Graphics Hardware 三维图形硬件中带宽减少的三角级深度滤波方法
2007 IEEE International Symposium on Circuits and Systems Pub Date : 2007-05-27 DOI: 10.1109/ISCAS.2007.377998
Jae-Sung Yoon, Chang-Hyo Yu, Donghyun Kim, L. Kim
{"title":"Triangle-Level Depth Filter Method for Bandwidth Reduction in 3D Graphics Hardware","authors":"Jae-Sung Yoon, Chang-Hyo Yu, Donghyun Kim, L. Kim","doi":"10.1109/ISCAS.2007.377998","DOIUrl":"https://doi.org/10.1109/ISCAS.2007.377998","url":null,"abstract":"In this paper, we proposed an early depth test method which extends a pixel-level depth filter to a triangle-level depth filter. This method decides whether the triangles are removed as well as pixels by a mask plane called depth filter (DF). The proposed method evaluates the DF in the triangle-level by using a hierarchical map of the conventional DF; thus the method removes the invisible triangles before the rasterization. Therefore, the rasterization performance can be increased and the bandwidth is further saved than the conventional DF. As the simulation results using complex scenes, the memory bandwidth is reduced by up to 31% compared with the conventional pixel-level DF method","PeriodicalId":274010,"journal":{"name":"2007 IEEE International Symposium on Circuits and Systems","volume":"106 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124117580","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Tiled Interleaving for Multi-Level 2-D Discrete Wavelet Transform 多层二维离散小波变换的平铺交织
2007 IEEE International Symposium on Circuits and Systems Pub Date : 2007-05-27 DOI: 10.1109/ISCAS.2007.378673
Jung-Wook Kim, Jinook Song, Seokho Lee, I. Park
{"title":"Tiled Interleaving for Multi-Level 2-D Discrete Wavelet Transform","authors":"Jung-Wook Kim, Jinook Song, Seokho Lee, I. Park","doi":"10.1109/ISCAS.2007.378673","DOIUrl":"https://doi.org/10.1109/ISCAS.2007.378673","url":null,"abstract":"This paper presents a new architecture of 2D discrete wavelet transform (DWT) proposed for JPEG 2000. In the proposed architecture, the image is segmented into tiles each of which is sequentially processed to minimize the size of buffers required to process 2D DWT, and multi-level DWTs are interleaved to reduce the size of the repeat buffer drastically. Compared to the conventional architecture, the overall memory size is reduced by 85% and 92% for 256 times 256 and 512 times 512 images, respectively. The proposed DWT processor needs only 5kB memory for 256 times 256 images, and operates at 250MHz in 0.25-mu technology.","PeriodicalId":274010,"journal":{"name":"2007 IEEE International Symposium on Circuits and Systems","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124212037","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
On a novel Hybrid LQ-MCS control strategy and its application to a DC motor 一种新型混合LQ-MCS控制策略及其在直流电机上的应用
2007 IEEE International Symposium on Circuits and Systems Pub Date : 2007-05-27 DOI: 10.1109/ISCAS.2007.378736
M. Bernardo, U. Montanaro, S. Santini
{"title":"On a novel Hybrid LQ-MCS control strategy and its application to a DC motor","authors":"M. Bernardo, U. Montanaro, S. Santini","doi":"10.1109/ISCAS.2007.378736","DOIUrl":"https://doi.org/10.1109/ISCAS.2007.378736","url":null,"abstract":"This paper is concerned with the investigation of a novel hybrid LQ-adaptive strategy based on the so called minimal control synthesis algorithm (MCS). A model reference MCS adaptive control scheme is implemented where the reference model is controlled via an LQ regulator. An additional supervisory control action updates on-line the reference model and the gains of the LQ control, switching between a control and an identification phase. The resulting hybrid LQ-MCS algorithm is validated on a representative case study.","PeriodicalId":274010,"journal":{"name":"2007 IEEE International Symposium on Circuits and Systems","volume":"85 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123624245","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
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