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2007 IEEE International Symposium on Circuits and Systems最新文献

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Compact, Low Power Wireless Sensor Network System for Line Crossing Recognition 用于线路交叉识别的小型低功耗无线传感器网络系统
2007 IEEE International Symposium on Circuits and Systems Pub Date : 2007-05-27 DOI: 10.1109/ISCAS.2007.378748
Chung-Ching Shen, R. Kupershtok, Bo Yang, F. Vanin, X. Shao, Datta Sheth, N. Goldsman, Q. Balzano, S. Bhattacharyya
{"title":"Compact, Low Power Wireless Sensor Network System for Line Crossing Recognition","authors":"Chung-Ching Shen, R. Kupershtok, Bo Yang, F. Vanin, X. Shao, Datta Sheth, N. Goldsman, Q. Balzano, S. Bhattacharyya","doi":"10.1109/ISCAS.2007.378748","DOIUrl":"https://doi.org/10.1109/ISCAS.2007.378748","url":null,"abstract":"Many application-specific wireless sensor network (WSN) systems require small size and low power features due to their limited resources, and their use in distributed, wireless environments. In this paper, we present a light-weight distributed algorithm for line-crossing recognition, together with its analysis, implementation, and experimental evaluation within a prototype wireless sensor network platform. The algorithm is developed in conjunction with a TDMA-based communication protocol such that the proposed system provides for low duty cycle and energy efficient operation. An accurate lifetime model is proposed with consideration of detailed energy usage to analyze and estimate the system lifetime. Our experimental results demonstrate the accuracy of this lifetime model, and its utility in optimizing network implementation. The design and experimental evaluation of our prototype network demonstrates the compactness and functionality of the proposed distributed WSN system for line-crossing recognition.","PeriodicalId":274010,"journal":{"name":"2007 IEEE International Symposium on Circuits and Systems","volume":"2 5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128451798","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Performance of Multi-User DCSK Communication System Over Multipath Fading Channels 多径衰落信道下多用户DCSK通信系统性能研究
2007 IEEE International Symposium on Circuits and Systems Pub Date : 2007-05-27 DOI: 10.1109/ISCAS.2007.378741
Zhibo Zhou, Tong Zhou, Jinxiang Wang
{"title":"Performance of Multi-User DCSK Communication System Over Multipath Fading Channels","authors":"Zhibo Zhou, Tong Zhou, Jinxiang Wang","doi":"10.1109/ISCAS.2007.378741","DOIUrl":"https://doi.org/10.1109/ISCAS.2007.378741","url":null,"abstract":"The bit error rate (BER) performances of an invariant delay multiple access DCSK (IDMA-DCSK) communication system over multipath fading channels are investigated. According to central limit theorem (CLT) we evaluate the BER formula of the IDMA-DCSK over Rayleigh and Ricean fading channels respectively. A two-ray fading channel model is used to simulate the IDMA-DCSK system. The theoretical and the simulation results match closely to each other, which supports the analyses approach.","PeriodicalId":274010,"journal":{"name":"2007 IEEE International Symposium on Circuits and Systems","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128779788","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
A novel voltage-clamped CMOS ISFET sensor interface 一种新型箝位CMOS ISFET传感器接口
2007 IEEE International Symposium on Circuits and Systems Pub Date : 2007-05-27 DOI: 10.1109/ISCAS.2007.378224
L. Shepherd, P. Georgiou, C. Toumazou
{"title":"A novel voltage-clamped CMOS ISFET sensor interface","authors":"L. Shepherd, P. Georgiou, C. Toumazou","doi":"10.1109/ISCAS.2007.378224","DOIUrl":"https://doi.org/10.1109/ISCAS.2007.378224","url":null,"abstract":"This paper presents a novel interface for ion-sensitive field effect transistors (ISFET) in which operation at a fixed electrical bias is achieved by voltage clamping. The chosen topology provides pH-dependent current and voltage output signals to drive an appropriate output stage. The circuit can be operated in either strong or weak inversion, depending on the requirements of the application with a pseudo-differential ISFET-REFET topology to allow use of an on-chip reference electrode. Simulation results are shown herein for single-ended and differential implementations. For a single-ended front-end with 1nA bias current, the strong inversion implementation at 2.5V supply has a power consumption of 0.185mW at pH 7 and the weak inversion implementation at 1.5V supply has a power consumption of 13nW at pH 7. The circuit and ISFET-REFET pair have been fabricated in the UMC 0.25mum CMOS technology.","PeriodicalId":274010,"journal":{"name":"2007 IEEE International Symposium on Circuits and Systems","volume":"59 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128279270","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 35
Theory and Implementation of an Analog-to-Information Converter using Random Demodulation 基于随机解调的模拟-信息转换器的理论与实现
2007 IEEE International Symposium on Circuits and Systems Pub Date : 2007-05-27 DOI: 10.1109/ISCAS.2007.378360
J. Laska, S. Kirolos, Marco F. Duarte, T. Ragheb, Richard Baraniuk, Y. Massoud
{"title":"Theory and Implementation of an Analog-to-Information Converter using Random Demodulation","authors":"J. Laska, S. Kirolos, Marco F. Duarte, T. Ragheb, Richard Baraniuk, Y. Massoud","doi":"10.1109/ISCAS.2007.378360","DOIUrl":"https://doi.org/10.1109/ISCAS.2007.378360","url":null,"abstract":"The new theory of compressive sensing enables direct analog-to-information conversion of compressible signals at sub-Nyquist acquisition rates. The authors develop new theory, algorithms, performance bounds, and a prototype implementation for an analog-to-information converter based on random demodulation. The architecture is particularly apropos for wideband signals that are sparse in the time-frequency plane. End-to-end simulations of a complete transistor-level implementation prove the concept under the effect of circuit nonidealities.","PeriodicalId":274010,"journal":{"name":"2007 IEEE International Symposium on Circuits and Systems","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124567233","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 436
A New CMOS 3.1-11.7 GHz Low Power LNA for Ultra-Wideband Wireless Applications 一种用于超宽带无线应用的新型CMOS 3.1-11.7 GHz低功耗LNA
2007 IEEE International Symposium on Circuits and Systems Pub Date : 2007-05-27 DOI: 10.1109/ISCAS.2007.378576
M. Reja, C. Sellathamby, I. Filanovsky
{"title":"A New CMOS 3.1-11.7 GHz Low Power LNA for Ultra-Wideband Wireless Applications","authors":"M. Reja, C. Sellathamby, I. Filanovsky","doi":"10.1109/ISCAS.2007.378576","DOIUrl":"https://doi.org/10.1109/ISCAS.2007.378576","url":null,"abstract":"In this paper, a new 3.1 GHz to 11.7 GHz ultra-wide-band (UWB) low-noise amplifier (LNA) is designed in 0.18-mum RF CMOS process. The proposed circuit includes a common-source cascode amplifier followed by an output buffer stage. Special attention is paid to design of inter-stage circuit employing the combined shunt and double-series inductive peaking bandwidth enhancement technique. The amplifier exhibits a forward gain (S21) of 11.0-11.5 dB, a noise figure (NF) of 3.6-4.4 dB, and input return loss (S11) of less than -9.3 dB over the frequency range of 3.1 GHz to 11.7 GHz while consuming only 6.2 mW from a power supply of 1.5 V.","PeriodicalId":274010,"journal":{"name":"2007 IEEE International Symposium on Circuits and Systems","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125137701","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
A Methodology for Efficient Space-Time Adapter Design Space Exploration: A Case Study of an Ultra Wide Band Interleaver 一种高效的时空适配器设计方法:以超宽带交织器为例
2007 IEEE International Symposium on Circuits and Systems Pub Date : 2007-05-27 DOI: 10.1109/ISCAS.2007.377867
C. Chavet, P. Coussy, P. Urard, E. Martin
{"title":"A Methodology for Efficient Space-Time Adapter Design Space Exploration: A Case Study of an Ultra Wide Band Interleaver","authors":"C. Chavet, P. Coussy, P. Urard, E. Martin","doi":"10.1109/ISCAS.2007.377867","DOIUrl":"https://doi.org/10.1109/ISCAS.2007.377867","url":null,"abstract":"This paper presents a solution to efficiently explore the design space of communication adapters. In most digital signal processing (DSP) applications, the overall architecture of the system is significantly affected by communication architecture, so the designers need specifically optimized adapters. By explicitly modeling these communications within an effective graph-theoretic model and analysis framework, we automatically generate an optimized architecture, named Space-Time AdapteR (STAR). Our design flow inputs a C description of input/output data scheduling, and user requirements (throughput, latency, parallelism...), and formalizes communication constraints through a resource constraints graph (RCG). The RCG properties enable an efficient architecture space exploration in order to synthesize a STAR component. The proposed approach has been tested to design an industrial data mixing block example: an ultra-wideband interleaver.","PeriodicalId":274010,"journal":{"name":"2007 IEEE International Symposium on Circuits and Systems","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129439640","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Watermarking for IP Protection through Template Substitution at Logic Synthesis Level 基于逻辑综合级模板替换的IP保护水印
2007 IEEE International Symposium on Circuits and Systems Pub Date : 2007-05-27 DOI: 10.1109/ISCAS.2007.378643
Aijiao Cui, Chip-Hong Chang
{"title":"Watermarking for IP Protection through Template Substitution at Logic Synthesis Level","authors":"Aijiao Cui, Chip-Hong Chang","doi":"10.1109/ISCAS.2007.378643","DOIUrl":"https://doi.org/10.1109/ISCAS.2007.378643","url":null,"abstract":"Functionality preservation and area-time overhead are two major concerns of VLSI designers when the watermarking technique is used to protect their intellectual property. For a given technology library and a logically synthesized circuit, replacing cells with the templates of the same function will not alter the topology and original function of the circuit but the performances of some datapaths may be affected. If the resultant circuit can still satisfy the synthesis constraints with an acceptably low overhead, watermarking through template substitution at logic synthesis level is feasible. In this paper, we propose an algorithm to select appropriate cells for the replacement to realize the watermarking scheme. The method is tested on a set of combinational MCNC benchmarks. The results show that this watermarking process can provide a sufficiently strong proof of authorship with trivial area overhead.","PeriodicalId":274010,"journal":{"name":"2007 IEEE International Symposium on Circuits and Systems","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130222005","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 15
Memory Access Reduced Software Implementation of H.264/AVC Sub-pixel Motion Estimation Using Differential Data Encoding 基于差分数据编码的H.264/AVC亚像素运动估计的软件实现
2007 IEEE International Symposium on Circuits and Systems Pub Date : 2007-05-27 DOI: 10.1109/ISCAS.2007.377855
Hyojin Choi, Wonchul Lee, Wonyong Sung
{"title":"Memory Access Reduced Software Implementation of H.264/AVC Sub-pixel Motion Estimation Using Differential Data Encoding","authors":"Hyojin Choi, Wonchul Lee, Wonyong Sung","doi":"10.1109/ISCAS.2007.377855","DOIUrl":"https://doi.org/10.1109/ISCAS.2007.377855","url":null,"abstract":"We studied an efficient software implementation of H.264/AVC sub-pixel motion estimation (ME) algorithm on a VLIW-SIMD digital signal processor, TMS320C6416. The sub-pixel ME algorithm demands large memory accesses while the required arithmetic operations are fairly simple. Although the CPU clock cycles for arithmetic operations can be reduced much by employing sub-word operations and applying software pipelining techniques, the limited memory bandwidth of the architecture restricts the overall performance. Moreover, aggressive VLIW-SIMD optimization results in the degradation of the performance by causing excessive CPU stalls during memory accesses. In this paper, we relieved the memory bandwidth requirements for creating quarter-pixel images by reducing the precision of image data, from 8 bits to 4 bits. As a result, the amount of memory accesses is much reduced at the cost of some increase of the arithmetic operations, which contributes to the balance of arithmetic and memory access operations. The experimental result shows that the memory stall cycles are decreased by 80% and the speed-up of 260% is obtained. The bit rate of the encoded video stream is increased slightly, about 2% on the average, due to the effects of quantization.","PeriodicalId":274010,"journal":{"name":"2007 IEEE International Symposium on Circuits and Systems","volume":"114 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130360992","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
An inverse method of characteristics for analyzing circuits with widely separated time-scales 具有广泛时间尺度的电路特性逆分析方法
2007 IEEE International Symposium on Circuits and Systems Pub Date : 2007-05-27 DOI: 10.1109/ISCAS.2007.378682
H. Brachtendorf, A. Bunse-Gerstner, B. Lang, R. Laur
{"title":"An inverse method of characteristics for analyzing circuits with widely separated time-scales","authors":"H. Brachtendorf, A. Bunse-Gerstner, B. Lang, R. Laur","doi":"10.1109/ISCAS.2007.378682","DOIUrl":"https://doi.org/10.1109/ISCAS.2007.378682","url":null,"abstract":"Widely separated time-scales occur in many radio-frequency (RF) circuits, making the analysis with standard numerical methods difficult and costly. Low and high frequency signals are often superimposed enforcing very small time-steps over a long time-period in the computation of the numerical solution. Hence, classical numerical techniques result into long runtimes. In this paper we present a general method of embedding the underlying system of ordinary differential-algebraic equations (DAEs) in a system of partial differential equations (PDEs), such that a restriction of the solution of the PDEs onto a suitable path yields the desired solution of the DAEs. This allows to treat contributions with different frequencies separately in different dimensions, each dimension representing a time-scale. Along the coordinates the solution of the PDEs is typically very smooth, making numerical techniques for the solution of PDEs highly efficient. Here, theoretical results as well as new numerical methods are presented","PeriodicalId":274010,"journal":{"name":"2007 IEEE International Symposium on Circuits and Systems","volume":"01 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130471983","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Convergence Analysis of the Unscented Kalman Filter for Filtering Noisy Chaotic Signals 无气味卡尔曼滤波滤波噪声混沌信号的收敛性分析
2007 IEEE International Symposium on Circuits and Systems Pub Date : 2007-05-27 DOI: 10.1109/ISCAS.2007.377916
Jiu-chao Feng, Hongjuan Fan, C. Tse
{"title":"Convergence Analysis of the Unscented Kalman Filter for Filtering Noisy Chaotic Signals","authors":"Jiu-chao Feng, Hongjuan Fan, C. Tse","doi":"10.1109/ISCAS.2007.377916","DOIUrl":"https://doi.org/10.1109/ISCAS.2007.377916","url":null,"abstract":"The unscented Kalman filter (UKF) has recently been proposed for filtering noisy chaotic signals. Though computationally advantageous, the UKF has not been thoroughly analyzed in terms of its convergence property. In this paper, non-periodic oscillatory behavior of the UKF when used to filter chaotic signals is reported. We show both theoretically and experimentally that the gain of the UKF may oscillate aperiodically. More precisely, when applied to periodic signals generated from nonlinear systems, the Kalman gain and error covariance of the UKF converge to zero. However, when the system being considered is chaotic, the Kalman gain either converges to a fixed point with a magnitude larger than zero or oscillates aperiodically.","PeriodicalId":274010,"journal":{"name":"2007 IEEE International Symposium on Circuits and Systems","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130515222","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
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