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2007 IEEE International Symposium on Circuits and Systems最新文献

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Variability-Aware Synthesis for Wideband Low Noise Amplifiers 宽带低噪声放大器的可变性感知合成
2007 IEEE International Symposium on Circuits and Systems Pub Date : 2007-05-27 DOI: 10.1109/ISCAS.2007.378157
Y. Massoud, A. Nieuwoudt, T. Ragheb
{"title":"Variability-Aware Synthesis for Wideband Low Noise Amplifiers","authors":"Y. Massoud, A. Nieuwoudt, T. Ragheb","doi":"10.1109/ISCAS.2007.378157","DOIUrl":"https://doi.org/10.1109/ISCAS.2007.378157","url":null,"abstract":"In this paper, we present a systematic synthesis methodology for fully integrated wideband low noise amplifiers (LNA) that simultaneously optimizes impedance matching, noise figure, and other performance parameters. Leveraging a wideband model, we hierarchically couple global optimization techniques with local convex optimization methods to efficiently locate circuits in the complex design space. The results indicate that the methodology can successfully generate wideband LNAs with various constraints on passive component values and performance metrics while providing the flexibility to reduce the impact of statistical process variations to improve both reliability and yield.","PeriodicalId":274010,"journal":{"name":"2007 IEEE International Symposium on Circuits and Systems","volume":"111 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131942624","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Localized closed-loop temperature control and regulation in hybrid silicon/silicone life science microsystems 混合硅/硅生命科学微系统的局部闭环温度控制和调节
2007 IEEE International Symposium on Circuits and Systems Pub Date : 2007-05-27 DOI: 10.1109/ISCAS.2007.377852
J. Christen, A. Andreou, B. Iglehart
{"title":"Localized closed-loop temperature control and regulation in hybrid silicon/silicone life science microsystems","authors":"J. Christen, A. Andreou, B. Iglehart","doi":"10.1109/ISCAS.2007.377852","DOIUrl":"https://doi.org/10.1109/ISCAS.2007.377852","url":null,"abstract":"We present hybrid silicon/silicone microsystem for closed-loop temperature control with applications in the life sciences. The system architecture includes an integrated CMOS die for localized thermal cycling and a disposable PDMS microfluidic structure for aseptic fluidic manipulation. Chip design, experimental results and finite element analysis are presented. This work is based on criteria for a clinical diagnostics system comprised of disposable microfluidics for use in tandem with CMOS electronics.","PeriodicalId":274010,"journal":{"name":"2007 IEEE International Symposium on Circuits and Systems","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131973668","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Approximate Frequency Response Models for RLC Power Grids RLC电网的近似频响模型
2007 IEEE International Symposium on Circuits and Systems Pub Date : 2007-05-27 DOI: 10.1109/ISCAS.2007.378785
D. Khalil, Y. Ismail
{"title":"Approximate Frequency Response Models for RLC Power Grids","authors":"D. Khalil, Y. Ismail","doi":"10.1109/ISCAS.2007.378785","DOIUrl":"https://doi.org/10.1109/ISCAS.2007.378785","url":null,"abstract":"Large power grid RLC models are complex and computationally expensive. This work explores the efficient modeling of power grid at early stages of the design with reduced complexity. This paper presents a simplified model of the power grid circuit based on the assumption of uniform load current distribution and equipotential nodes approximation. In addition, based on the moment matching technique an approximate analytical model is derived. The presented models provide huge reduction in complexity without scarifying much accuracy in the trans-impedance frequency response compared to the full RLC power grid model. This is desirable in the early phases of design where only initial estimates of load currents are available. The analytical model presented can be easily used for power grid optimization and trade-offs.","PeriodicalId":274010,"journal":{"name":"2007 IEEE International Symposium on Circuits and Systems","volume":" 11","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132040781","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
A Difference Based Adder Graph Heuristic for Multiple Constant Multiplication Problems 多常数乘法问题的差分加法图启发式算法
2007 IEEE International Symposium on Circuits and Systems Pub Date : 2007-05-27 DOI: 10.1109/ISCAS.2007.378201
O. Gustafsson
{"title":"A Difference Based Adder Graph Heuristic for Multiple Constant Multiplication Problems","authors":"O. Gustafsson","doi":"10.1109/ISCAS.2007.378201","DOIUrl":"https://doi.org/10.1109/ISCAS.2007.378201","url":null,"abstract":"Multiple constant multiplication (MCM), i.e., realizing a number of constant multiplications using a minimum number of adders and subtracters, has been an active research area for the last decade. An adder graph type algorithm for solving the MCM problem is introduced with a novel heuristic inspired by difference methods. It is shown that the results is as good or better as previous state of the art under most conditions. Furthermore, the proposed algorithm does not rely on look-up tables.","PeriodicalId":274010,"journal":{"name":"2007 IEEE International Symposium on Circuits and Systems","volume":"236 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132126068","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 123
Two-Stage OTA Design Based on Settling-Time Constraints 基于沉降时间约束的两阶段OTA设计
2007 IEEE International Symposium on Circuits and Systems Pub Date : 2007-05-27 DOI: 10.1109/ISCAS.2007.378565
G. Giustolisi
{"title":"Two-Stage OTA Design Based on Settling-Time Constraints","authors":"G. Giustolisi","doi":"10.1109/ISCAS.2007.378565","DOIUrl":"https://doi.org/10.1109/ISCAS.2007.378565","url":null,"abstract":"The transient response of a feedback two-stage OTA is analyzed in terms of slew-rate and gain-bandwidth product. An expression for the settling time is carried out. The results are then used to propose a design procedure for the two-stage OTA. The procedure is based on \"settling time constraint\" and on the use of the gm-over-ID ratio so to maximize the nodes voltage swing. The theory is validated by means of simulations and so is done for the design procedure.","PeriodicalId":274010,"journal":{"name":"2007 IEEE International Symposium on Circuits and Systems","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132352077","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Synthesis of Finite State Machines with Magnetic Domain Wall Logic 具有磁畴壁逻辑的有限状态机综合
2007 IEEE International Symposium on Circuits and Systems Pub Date : 2007-05-27 DOI: 10.1109/ISCAS.2007.378239
Jacques-Olivier Klein, E. Belhaire, C. Chappert, F. Ouchet, R. Cowburn, D. Read, D. Petit
{"title":"Synthesis of Finite State Machines with Magnetic Domain Wall Logic","authors":"Jacques-Olivier Klein, E. Belhaire, C. Chappert, F. Ouchet, R. Cowburn, D. Read, D. Petit","doi":"10.1109/ISCAS.2007.378239","DOIUrl":"https://doi.org/10.1109/ISCAS.2007.378239","url":null,"abstract":"As the feasibility of basic logic operators based on magnetic domain wall (MDW) logic has been demonstrated we present here the synthesis of more complex functions using this technology. After the presentation of the specific design constraints associated to MDW logic, we describe the architecture of finite state machines and show simulation results for a 3-bit counter.","PeriodicalId":274010,"journal":{"name":"2007 IEEE International Symposium on Circuits and Systems","volume":"107 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132424760","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
An Integrated Patch-Clamp Amplifier for High-Density Whole-Cell Recordings 用于高密度全细胞记录的集成膜片钳放大器
2007 IEEE International Symposium on Circuits and Systems Pub Date : 2007-05-27 DOI: 10.1109/ISCAS.2007.378324
P. Weerakoon, K. Klemic, F. Sigworth, E. Culurciello
{"title":"An Integrated Patch-Clamp Amplifier for High-Density Whole-Cell Recordings","authors":"P. Weerakoon, K. Klemic, F. Sigworth, E. Culurciello","doi":"10.1109/ISCAS.2007.378324","DOIUrl":"https://doi.org/10.1109/ISCAS.2007.378324","url":null,"abstract":"We fabricated an integrated patch-clamp amplifier capable of recording nano-amperes of current in whole-cell patch recording. Patch-clamp amplifiers presently consist of a head-stage and a large controller box that contains many hundreds of components. Our design compresses the function of the head-stage and the controller box into one chip that can be mounted near the patch-clamp electrode and can be controlled through a high-speed serial bus paving the way for higher densities in parallel patch-clamp systems. We report on the electrical measurements from the fabricated device.","PeriodicalId":274010,"journal":{"name":"2007 IEEE International Symposium on Circuits and Systems","volume":"75 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129964038","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
Low-Voltage Wilson Current Mirrors in CMOS CMOS中的低压威尔逊电流镜
2007 IEEE International Symposium on Circuits and Systems Pub Date : 2007-05-27 DOI: 10.1109/ISCAS.2007.378723
B. Minch
{"title":"Low-Voltage Wilson Current Mirrors in CMOS","authors":"B. Minch","doi":"10.1109/ISCAS.2007.378723","DOIUrl":"https://doi.org/10.1109/ISCAS.2007.378723","url":null,"abstract":"In this paper, we describe three simple low-voltage CMOS analogs of the Wilson current mirror that function well at all current levels, ranging from weak inversion to strong inversion. Each of these current mirrors can operate on a low power-supply voltage of a diode drop plus two saturation voltages and features a wide output-voltage swing with a cascode-type incremental output impedance. Two of the circuits requires an input voltage of a diode drop plus a saturation voltage while the third one features a low input voltage of a saturation voltage. We present experimental results from versions of these three current mirrors that were fabricated in a 0.5-mum CMOS process through MOSIS, comparing them with CMOS implementations of the conventional Wilson and super-Wilson current mirrors.","PeriodicalId":274010,"journal":{"name":"2007 IEEE International Symposium on Circuits and Systems","volume":"62 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130174694","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 37
A Microwave OTA Using a Feedforward-Regulated Cascode Topology 基于前馈调节级联码拓扑的微波OTA
2007 IEEE International Symposium on Circuits and Systems Pub Date : 2007-05-27 DOI: 10.1109/ISCAS.2007.378284
You Zheng, C. Saavedra
{"title":"A Microwave OTA Using a Feedforward-Regulated Cascode Topology","authors":"You Zheng, C. Saavedra","doi":"10.1109/ISCAS.2007.378284","DOIUrl":"https://doi.org/10.1109/ISCAS.2007.378284","url":null,"abstract":"A CMOS operational transconductance amplifier (OTA) with a novel feedforward-regulated cascode topology is proposed and experimentally demonstrated in this paper. It enables high-speed operation of the proposed OTA up to 8 GHz. For demonstration purposes, a microwave variable resistor and a variable active inductor using this OTA were fabricated using 0.18 mum CMOS process. Experimental results show that this OTA has a relatively high transconductance of about 10.5 mA/V at frequencies up to 8 GHz, with a tuning ratio of 1:5.3. The fabricated active inductor can achieve over 4.7 nH inductance at GHz frequencies and an inductance tuning ratio of 1:3.6 for microwave applications. The OTA basic cell integrated circuit measures 145times67 mum2, excluding bonding pads.","PeriodicalId":274010,"journal":{"name":"2007 IEEE International Symposium on Circuits and Systems","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130260134","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 15
FPGA Implementation of an Interpolation Processor for Soft-Decision Decoding of Reed-Solomon Codes 里德-所罗门码软判决译码插值处理器的FPGA实现
2007 IEEE International Symposium on Circuits and Systems Pub Date : 2007-05-27 DOI: 10.1109/ISCAS.2007.378513
Qinqin Chen, Zhongfeng Wang, Jun Ma
{"title":"FPGA Implementation of an Interpolation Processor for Soft-Decision Decoding of Reed-Solomon Codes","authors":"Qinqin Chen, Zhongfeng Wang, Jun Ma","doi":"10.1109/ISCAS.2007.378513","DOIUrl":"https://doi.org/10.1109/ISCAS.2007.378513","url":null,"abstract":"This paper presents an FPGA implementation of a high-speed interpolation processor for algebraic soft-decision decoding of Reed-Solomon codes. In the design, pipelining and parallel processing techniques are exploited to increase the decoding throughput. In addition, different parts of the interpolation processor are properly scheduled to achieve maximum overlap in processing time for the computations occurring at adjacent iterations. Synthesis results show that the FPGA implementation of the interpolation architecture can achieve a throughput of 149Mbps, which is multiple times higher than conventional design.","PeriodicalId":274010,"journal":{"name":"2007 IEEE International Symposium on Circuits and Systems","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134555128","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
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