Proceedings. 1998 International Conference on Parallel Architectures and Compilation Techniques (Cat. No.98EX192)最新文献_第3页

MADELEINE: an efficient and portable communication interface for RPC-based multithreaded environments MADELEINE:为基于rpc的多线程环境提供的高效、便携的通信接口

Proceedings. 1998 International Conference on Parallel Architectures and Compilation Techniques (Cat. No.98EX192) Pub Date : 1998-10-12 DOI: 10.1109/PACT.1998.727257

L. Bougé, J. Méhaut, R. Namyst

引用次数: 25

Efficient edge profiling for ILP-processors 用于ilp处理器的高效边缘分析

Proceedings. 1998 International Conference on Parallel Architectures and Compilation Techniques (Cat. No.98EX192) Pub Date : 1998-10-12 DOI: 10.1109/PACT.1998.727264

A. Eichenberger, S. M. Lobo

引用次数: 9

Improving static branch prediction in a compiler 改进编译器中的静态分支预测

Proceedings. 1998 International Conference on Parallel Architectures and Compilation Techniques (Cat. No.98EX192) Pub Date : 1998-10-12 DOI: 10.1109/PACT.1998.727253

B. Deitrich, B. Cheng, W. Hwu

{"title":"Improving static branch prediction in a compiler","authors":"B. Deitrich, B. Cheng, W. Hwu","doi":"10.1109/PACT.1998.727253","DOIUrl":"https://doi.org/10.1109/PACT.1998.727253","url":null,"abstract":"An ILP (Instruction-Level Parallelism) compiler uses aggressive optimizations to reduce a program's running time. These optimizations have been shown to be effective when profile information is available. Unfortunately, users are not always willing or able to profile their programs. A method of overcoming this issue is for an ILP compiler to statically infer the information normally obtained from profiling. This paper investigates one aspect of this inference: the static prediction of conditional-branch direction. The goals of this work are to utilize the source-level information available in a compiler when performing static branch prediction, to identify static-branch-prediction cases in which there is a high confidence that a branch will go in one direction at run time, to gain an intuitive understanding into the reasons why the static-branch-prediction heuristics are effective, and ultimately to improve the accuracy of the static branch prediction. The effectiveness of the static-branch-prediction heuristics developed in this paper is demonstrated on a set of programs from SPEC CINT92, SPEC CINT95, and the IMPACT compiler.","PeriodicalId":273746,"journal":{"name":"Proceedings. 1998 International Conference on Parallel Architectures and Compilation Techniques (Cat. No.98EX192)","volume":"258 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-10-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128885747","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 28

Code generation in the polytope model 多面体模型中的代码生成

Proceedings. 1998 International Conference on Parallel Architectures and Compilation Techniques (Cat. No.98EX192) Pub Date : 1998-10-12 DOI: 10.1109/PACT.1998.727179

M. Griebl, C. Lengauer, Sabine Wetzel

引用次数: 77

A fast algorithm for scheduling time-constrained instructions on processors with ILP 具有ILP的处理器上调度时间约束指令的快速算法

Proceedings. 1998 International Conference on Parallel Architectures and Compilation Techniques (Cat. No.98EX192) Pub Date : 1998-10-12 DOI: 10.1109/PACT.1998.727188

Allen Leung, K. Palem, A. Pnueli

{"title":"A fast algorithm for scheduling time-constrained instructions on processors with ILP","authors":"Allen Leung, K. Palem, A. Pnueli","doi":"10.1109/PACT.1998.727188","DOIUrl":"https://doi.org/10.1109/PACT.1998.727188","url":null,"abstract":"Instruction scheduling is central to achieving performance in modern processors with instruction level parallelism (ILP). Classical work in this area has spanned the theoretical foundations of algorithms for instruction scheduling with provable optimality, as well as heuristic approaches with experimentally validated performance improvements. Typically, the theoretical foundations are developed in the context of basic-blocks of code. In this paper, we provide the theoretical foundations for scheduling basic-blocks of instructions with time-constraints, which can play an important role in compile-time ILP optimizations in embedded applications. We present an algorithm for scheduling unit-execution-time instructions on machines with multiple pipelines, in the presence of precedence constraints, release-times, deadlines, and latencies l/sub ij/ between any pairs of instructions i and j. Our algorithm runs in time O(n/sup 3//spl alpha/(n)), where /spl alpha/(n) is the functional inverse of the Ackermann function. It can be used construct feasible schedules for two classes of instances: (1) one pipeline and the latencies between instructions are restricted to the values of 0 and 1, and (2) arbitrary number of pipelines and monotone-interval order precedences. Our result can be seen as a natural extension of previous work on instruction scheduling for pipelined machines in the presence of deadlines.","PeriodicalId":273746,"journal":{"name":"Proceedings. 1998 International Conference on Parallel Architectures and Compilation Techniques (Cat. No.98EX192)","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-10-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124358181","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 14

Integrated compilation and scalability analysis for parallel systems 并行系统的集成编译与可扩展性分析

Proceedings. 1998 International Conference on Parallel Architectures and Compilation Techniques (Cat. No.98EX192) Pub Date : 1998-10-12 DOI: 10.1109/PACT.1998.727287

C. Mendes, D. Reed

引用次数: 42

Efficacy and performance impact of value prediction 效能与绩效影响价值预测

Proceedings. 1998 International Conference on Parallel Architectures and Compilation Techniques (Cat. No.98EX192) Pub Date : 1998-10-12 DOI: 10.1109/PACT.1998.727186

Bohuslav Rychlik, John Faistl, Bryon Krug, John Paul Shen

引用次数: 95

General parallel computation can be performed with a cycle-free heap 一般的并行计算可以用无循环堆来执行

Proceedings. 1998 International Conference on Parallel Architectures and Compilation Techniques (Cat. No.98EX192) Pub Date : 1998-10-12 DOI: 10.1109/PACT.1998.727177

J. Dennis

引用次数: 10

A new heuristic for scheduling parallel programs on multiprocessor 一种新的多处理机并行程序调度启发式算法

Proceedings. 1998 International Conference on Parallel Architectures and Compilation Techniques (Cat. No.98EX192) Pub Date : 1998-10-12 DOI: 10.1109/PACT.1998.727277

Jing-Chiou Liou, M. Palis

引用次数: 21

Command vector memory systems: high performance at low cost 指令矢量存储器系统:低成本的高性能

Proceedings. 1998 International Conference on Parallel Architectures and Compilation Techniques (Cat. No.98EX192) Pub Date : 1998-10-12 DOI: 10.1109/PACT.1998.727154

J. Corbal, R. Espasa, M. Valero

{"title":"Command vector memory systems: high performance at low cost","authors":"J. Corbal, R. Espasa, M. Valero","doi":"10.1109/PACT.1998.727154","DOIUrl":"https://doi.org/10.1109/PACT.1998.727154","url":null,"abstract":"The focus of this paper is on designing both a low cost and high performance, high bandwidth vector memory system that takes advantage of modern commodity SDRAM memory chips. To successfully extract the full bandwidth from SDRAM parts, we propose a new memory system organization based on sending commands to the memory system as opposed to sending individual addresses. A command specifies, in a few bytes, a request for multiple independent memory words. A command is similar to a burst found in DRAM memories, but does not require the memory words to be consecutive. The command is sent to all sections of the memory array simultaneously, thus not requiring a crossbar in the proper sense. Our simulations show that this command based memory system can improve performance over a traditional SDRAM-based memory system by factors that range between 1.15 up to 1.54. Moreover, in many cases, the command memory system outperforms even the best SRAM memory system under consideration. Overall the command based memory system achieves similar or better results than a 10 ns SRAM memory system (a) using fewer banks and (b) using memory devices that are between 15 to 60 times cheaper.","PeriodicalId":273746,"journal":{"name":"Proceedings. 1998 International Conference on Parallel Architectures and Compilation Techniques (Cat. No.98EX192)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-10-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131324589","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 60