Proceedings. 1998 International Conference on Parallel Architectures and Compilation Techniques (Cat. No.98EX192)最新文献

筛选
英文 中文
A new framework for integrated global local scheduling 一种新的集成全局局部调度框架
S. Mantripragada, S. Jain, James C. Dehnert
{"title":"A new framework for integrated global local scheduling","authors":"S. Mantripragada, S. Jain, James C. Dehnert","doi":"10.1109/PACT.1998.727189","DOIUrl":"https://doi.org/10.1109/PACT.1998.727189","url":null,"abstract":"Global Instruction Schedulers can be classified as either structure or profile driven. Structure driven approaches attempt to find instruction level parallelism by redistributing instructions along all possible execution paths. When resources are limited, poor choices may penalize the frequently executed paths. By contrast, profile driven approaches use feedback information to identify frequently executed (hot) regions, and attempt to improve their performance. This may be at the expense of less frequently executed (cold) regions, for instance by inserting fixup code. The overall performance improves if the frequency information is accurate and there is a dominant trace in the program. If either of these conditions does not hold, performance may degrade. We present a novel algorithm that attempts to combine the individual merits of the above two approaches while avoiding some of their drawbacks. We have also incorporated several techniques which improve the global scheduling performance on out-of-order (OOO) processors. Our algorithm is integrated with a parametric resource model and can be applied both before and after register allocation. It has been implemented in the SGI MIPSpro compiler, and the results have been evaluated on the MIPS R8000 and R10000 processors.","PeriodicalId":273746,"journal":{"name":"Proceedings. 1998 International Conference on Parallel Architectures and Compilation Techniques (Cat. No.98EX192)","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-10-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115289355","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 18
Breaking the barriers: two models for MPI programming 打破障碍:两种MPI编程模型
J. R. García, C. Rodríguez, Daniel González-Morales, F. Almeida, Pablo Pulido, Daniel Dorta
{"title":"Breaking the barriers: two models for MPI programming","authors":"J. R. García, C. Rodríguez, Daniel González-Morales, F. Almeida, Pablo Pulido, Daniel Dorta","doi":"10.1109/PACT.1998.727258","DOIUrl":"https://doi.org/10.1109/PACT.1998.727258","url":null,"abstract":"The asynchronous nature of many MPI/PVM programs does not fit the BSP model. The barrier synchronization imposed by the model restricts the range of available algorithms and their performance. Through the suppression of barriers and the generalization of the concept of superstep we propose two new models, the BSP-like and the BSP Without Barriers (BSPWB) models. While the BSP-like extends the BSP* model to programs written using collective operations, the more general BSPWB model admits the MPI/PVM parallel asynchronous programming style. As LogP, the model encourages locality but it is simpler to use. The parameters of the models and their quality are evaluated on a distributed shared memory machine, the Origin 2000 and on a distributed memory machine, the CRAY T3E. The dependence of the time spent in an h-relation is stronger in the communication pattern than in the number of processors. The total variation of the h-relation time in both the patterns and processor numbers is smaller than sixty nanoseconds. To illustrate the proposed models, two different applications are considered: a Parallel Sort using Regular Sampling (PSRS) and a Parallel Dynamic Programming Algorithm solving the Single Resource Allocation Problem (SRAP). The PSRS is a synchronous algorithm with a rich set of collective communication patterns and coarse grain communications. On the opposite extreme, the SRAP is a fine grain communication algorithm using permutation patterns. The computational results prove the accuracy of the models. The prediction of the communication times is robust even for the SRAP, where communication is dominated by small messages.","PeriodicalId":273746,"journal":{"name":"Proceedings. 1998 International Conference on Parallel Architectures and Compilation Techniques (Cat. No.98EX192)","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-10-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122565734","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Capturing the effects of code improving transformations 获取代码改进转换的效果
Clara Jaramillo, Rajiv Gupta, M. Soffa
{"title":"Capturing the effects of code improving transformations","authors":"Clara Jaramillo, Rajiv Gupta, M. Soffa","doi":"10.1109/PACT.1998.727181","DOIUrl":"https://doi.org/10.1109/PACT.1998.727181","url":null,"abstract":"Symbolic debugging of transformed code requires information about the impact of applying transformations on statement instances so that the appropriate values can be displayed to a user. We present a technique to automatically identify statement instance correspondences between untransformed and transformed code and generate mappings reflecting these correspondences as code improving transformations are applied. The mappings support classical optimizations as well as loop transformations. Establishing mappings requires analyzing how the position, number, and order of instances of a statement can change in a particular context when transformations are applied. In addition to enabling symbolic debugging of transformed code, these mappings can be used to understand transformed code and to compare values computed in both program versions either manually or automatically.","PeriodicalId":273746,"journal":{"name":"Proceedings. 1998 International Conference on Parallel Architectures and Compilation Techniques (Cat. No.98EX192)","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-10-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127676917","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 19
Improving cache behavior of dynamically allocated data structures 改进动态分配数据结构的缓存行为
D. Truong, F. Bodin, André Seznec
{"title":"Improving cache behavior of dynamically allocated data structures","authors":"D. Truong, F. Bodin, André Seznec","doi":"10.1109/PACT.1998.727268","DOIUrl":"https://doi.org/10.1109/PACT.1998.727268","url":null,"abstract":"Poor data layout in memory may generate weak data locality and poor performance. Code transformations such as loop blocking or interchanging and array padding have addressed this issue for scientific applications. However many generalist applications do not use data arrays, but dynamically allocated heterogeneous data structures. In this paper, we explore two data layout techniques for dynamically allocated data structures: field reorganization, and instance interleaving. The application of these techniques may be guided by program profiling. This allows significant cache behavior improvements on some applications. To support instance interleaving, we developed a specific memory allocation library called ialloc. An ialloc-like library may be of great help in a toolbox for performance tuning of general-purpose applications.","PeriodicalId":273746,"journal":{"name":"Proceedings. 1998 International Conference on Parallel Architectures and Compilation Techniques (Cat. No.98EX192)","volume":"2 3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-10-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132117292","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 113
Exploiting method-level parallelism in single-threaded Java programs 在单线程Java程序中利用方法级并行性
Michael K. Chen, K. Olukotun
{"title":"Exploiting method-level parallelism in single-threaded Java programs","authors":"Michael K. Chen, K. Olukotun","doi":"10.1109/PACT.1998.727190","DOIUrl":"https://doi.org/10.1109/PACT.1998.727190","url":null,"abstract":"Method speculation of object-oriented programs attempts to exploit method-level parallelism (MLP) by executing sequential method invocations in parallel, while still maintaining correct sequential ordering of data dependencies and memory accesses. In this paper, we show why the Java virtual machine is an effective environment for exploiting method-level parallelism, and demonstrate how method speculation can potentially speed up single-threaded general purpose Java programs. Results from our study show that significant speedups can be achieved on data-parallel applications with minimal programmer and compiler effort. On control-flow dependent programs, moderate speedups have been achieved, suggesting more significant performance improvements on these types of programs may come from more careful analysis or re-coding of the application. For both classes of applications, we discover performance debugging drastically improves speedups by eliminating or minimizing dependencies that limit the effectiveness of method speculation.","PeriodicalId":273746,"journal":{"name":"Proceedings. 1998 International Conference on Parallel Architectures and Compilation Techniques (Cat. No.98EX192)","volume":"88 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-10-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134059264","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 86
Parallelization of benchmarks for scalable shared-memory multiprocessors 可扩展共享内存多处理器基准的并行化
Y. Paek, A. Navarro, E. Zapata, D. Padua
{"title":"Parallelization of benchmarks for scalable shared-memory multiprocessors","authors":"Y. Paek, A. Navarro, E. Zapata, D. Padua","doi":"10.1109/PACT.1998.727292","DOIUrl":"https://doi.org/10.1109/PACT.1998.727292","url":null,"abstract":"This paper identifies practical compiling techniques for scalable shared memory machines. For this, we have focused on experimental studies using a real machine and representative codes. In the experiments, we transformed conventional codes to shared memory codes using several existing techniques and ran the output on the target machine to evaluate those techniques and to identify where improvement is needed. Based on the analysis of the results, we developed a few new techniques, and experimented again on the target machine to measure the effectiveness of each one. The results reported in this paper were quite positive, lending useful information to future research on compiler optimizations for existing SSM machines.","PeriodicalId":273746,"journal":{"name":"Proceedings. 1998 International Conference on Parallel Architectures and Compilation Techniques (Cat. No.98EX192)","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-10-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128925222","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Split last-address predictor 分割最后地址预测器
E. Morancho, J. Llabería, À. Olivé
{"title":"Split last-address predictor","authors":"E. Morancho, J. Llabería, À. Olivé","doi":"10.1109/PACT.1998.727255","DOIUrl":"https://doi.org/10.1109/PACT.1998.727255","url":null,"abstract":"Recent works have proposed the use of prediction techniques to execute speculatively true data-dependent operations. However, the predictability of the operations do not spread uniformly among them. Then, we propose the use of run-time classification of instructions to increase the efficiency of the predictors. At run time, the proposed mechanism classifies instructions according to their predictability, decoupling this classification from prediction table. Then, the classification is used to avoid the unpredictable instructions from being candidates to allocate an entry in the prediction table. The previous idea of run-time classification is applied to the last-address predictor (Split Last-Address Predictor). The goal of this predictor is to reduce the latency of load instructions. Memory access is performed after the effective address is predicted concurrently with instruction fetch, after that, next true data-dependent instructions can be executed speculatively. We show that our proposal applied to the last-address predictor captures the same predictability than the last-address predictor proposed in literature, increases its accuracy, and reduces its area-cost by 19%.","PeriodicalId":273746,"journal":{"name":"Proceedings. 1998 International Conference on Parallel Architectures and Compilation Techniques (Cat. No.98EX192)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-10-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115731866","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 20
The START-VOYAGER parallel system START-VOYAGER平行系统
B. S. Ang, Derek Chiou, L. Rudolph, Arvind
{"title":"The START-VOYAGER parallel system","authors":"B. S. Ang, Derek Chiou, L. Rudolph, Arvind","doi":"10.1109/PACT.1998.727191","DOIUrl":"https://doi.org/10.1109/PACT.1998.727191","url":null,"abstract":"This paper presents the communication architecture of the START-VOYAGER system, a parallel machine composed of a cluster of unmodified IBM 604e-based SMP's connected via a high speed interconnection network. A custom network interface unit (NIU) plugs into a processor card slot of each SMP, providing a high-performance message passing substrate that supports both fast user-level message passing and cache-line coherent shared memory. The substrate consists of four hardware implemented message passing mechanisms to achieve high performance over a wide spectrum of communication patterns. START-VOYAGER also introduces a novel protection scheme which improves upon past designs by not requiring strictly synchronized gang-scheduling and by allowing system code and multiple user applications to share the network simultaneously without compromising protection nor performance. Performance predictions based on synthesized Verilog code show START-VOYAGER's novel message passing mechanisms offer a definitive advantage in a multi-threaded environment without compromising the performance in a single-threaded environment. Preliminary shared memory simulations are also promising.","PeriodicalId":273746,"journal":{"name":"Proceedings. 1998 International Conference on Parallel Architectures and Compilation Techniques (Cat. No.98EX192)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-10-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124035675","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 13
Adaptive scheduling of computations and communications on distributed memory systems 分布式存储系统上计算和通信的自适应调度
M. Al-Mouhamed, Homam Najjari
{"title":"Adaptive scheduling of computations and communications on distributed memory systems","authors":"M. Al-Mouhamed, Homam Najjari","doi":"10.1109/PACT.1998.727281","DOIUrl":"https://doi.org/10.1109/PACT.1998.727281","url":null,"abstract":"Compile-time scheduling is one approach to extract parallelism which proved to be effective when the execution behavior is predictable. Unfortunately, the performance of most priority-based scheduling algorithms is computation dependent. Scheduling by using earliest-task-first (ETF) produces reasonably short schedules only when available parallelism is large enough to cover the communications. A priority-based decision is much more effective when parallelism is low. We propose a scheduling in which the decision function combines: (1) task-level as global priority, and (2) earliest-task-first as local priority. The degree of dominance of one of the above concepts is controlled by a computation profile factor such as task parallelism and communication. An iterative scheduler (forward and backward) is proposed for tuning the solution. In each iteration, the new schedule is used to sharpen the task-levels. This contributes in finding shorter schedules in next iteration. Evaluation is carried out by using synthetic task-graphs for computations with communications times for which optimum schedules are known. It is found that finish time of pure local scheduling (like ETF) and static priority-based scheduling significantly deviate from optimum when task parallelism is low in presence of relatively large communication. Our approach to adapting the scheduling decision to computation profile was able to produce near-optimum solutions through much less number of iterations than other approaches.","PeriodicalId":273746,"journal":{"name":"Proceedings. 1998 International Conference on Parallel Architectures and Compilation Techniques (Cat. No.98EX192)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-10-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125675391","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Dynamic hammock predication for non-predicated instruction set architectures 非谓词指令集架构的动态吊床预测
A. Klauser, T. Austin, D. Grunwald, B. Calder
{"title":"Dynamic hammock predication for non-predicated instruction set architectures","authors":"A. Klauser, T. Austin, D. Grunwald, B. Calder","doi":"10.1109/PACT.1998.727261","DOIUrl":"https://doi.org/10.1109/PACT.1998.727261","url":null,"abstract":"Conventional speculative architectures use branch prediction to evaluate the most likely execution path during program execution. However certain branches are difficult to predict. One solution to this problem is to evaluate both paths following such a conditional branch. Predicated execution can be used to implement this form of multi-path execution. Predicated architectures fetch and issue instructions that have associated predicates. These predicates indicate if the instruction should commit its result. Predicating a branch reduces the number of branches executed, eliminating the chance of branch misprediction at the cost of executing additional instructions. In this paper, we propose a restricted form of multi-path execution called Dynamic Predication for architectures with little or no support for predicated instructions in their instruction set. Dynamic predication dynamically predicates instruction sequences in the form of a branch hammock concurrently executing both paths of the branch. A branch hammock is a short forward branch that spans a few instructions in the form of an if-then or if-then-else construct we mark these and other constructs in the executable. When the decode stage detects such a sequence, it passes a predicated instruction sequence to a dynamically scheduled execution core. Our results show that dynamic predication can accrue speedups of up to 13%.","PeriodicalId":273746,"journal":{"name":"Proceedings. 1998 International Conference on Parallel Architectures and Compilation Techniques (Cat. No.98EX192)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-10-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130269851","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 64
0
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
提示
您的信息不完整,为了账户安全,请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
确定
请完成安全验证×
相关产品
×
本文献相关产品
联系我们:info@booksci.cn Book学术提供免费学术资源搜索服务,方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。 Copyright © 2023 布克学术 All rights reserved.
京ICP备2023020795号-1
ghs 京公网安备 11010802042870号
Book学术文献互助
Book学术文献互助群
群 号:604180095
Book学术官方微信
小红书