{"title":"Fast, accurate and flexible data locality analysis","authors":"F. Sánchez, Antonio González","doi":"10.1109/PACT.1998.727182","DOIUrl":"https://doi.org/10.1109/PACT.1998.727182","url":null,"abstract":"This paper presents a tool based on a new approach for analyzing the locality exhibited by data memory references. The tool is very fast because it is based on a static locality analysis enhanced with very simple profiling information, which results in a negligible slowdown. This feature allows the tool to be used for highly time-consuming applications and to include it as a step in a typical iterative analysis-optimization process. The tool can provide a detailed evaluation of the reuse exhibited by a program, quantifying and qualifying the different types of misses either globally or detailed by program sections, data structures, memory instructions, etc. The accuracy of the tool is validated by comparing its results with those provided by a simulator.","PeriodicalId":273746,"journal":{"name":"Proceedings. 1998 International Conference on Parallel Architectures and Compilation Techniques (Cat. No.98EX192)","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-10-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132677712","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Efficient JavaVM just-in-time compilation","authors":"A. Krall","doi":"10.1109/PACT.1998.727250","DOIUrl":"https://doi.org/10.1109/PACT.1998.727250","url":null,"abstract":"Conventional compilers are designed for producing highly optimized code without paying much attention to compile time. The design goals of Java just-in-time compilers are different: produce fast code at the smallest possible compile time. In this article we present a very fast algorithm for translating JavaVM byte code to high quality machine code for RISC processors. This algorithm handles combines instructions, does copy elimination and coalescing and does register allocation. It comprises three passes: basic block determination, stack analysis and register preallocation, final register allocation and machine code generation. This algorithm replaces an older one in the CACAO JavaVM implementation reducing the compile time by a factor of seven and producing slightly faster machine code. The speedup comes mainly from following simplifications: fixed assignment of registers at basic block boundaries, simple register allocator better exception handling better memory management and fine tuning the implementation. The CACAO system is currently faster than every JavaVM implementation for the Alpha processor and generates machine code for all used methods of the javac compiler and its libraries in 60 milliseconds on an Alpha workstation.","PeriodicalId":273746,"journal":{"name":"Proceedings. 1998 International Conference on Parallel Architectures and Compilation Techniques (Cat. No.98EX192)","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-10-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121166126","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Eliminating bottlenecks on parallel systems using adaptive objects","authors":"M. Yasugi, Shegeyuki Eguchi, K. Taki","doi":"10.1109/PACT.1998.727175","DOIUrl":"https://doi.org/10.1109/PACT.1998.727175","url":null,"abstract":"Dynamic method replacement is a new technique to eliminate bottlenecks (e.g., around a root of tree structure) using adaptive objects for concurrent accesses. The technique eliminates the frequency of mutual exclusion and remote message passing by dynamically increasing the number of read only methods and the immutable part of objects. The results of performance measurements on both shared memory and distributed memory parallel architectures indicate the effectiveness of our approach to bottleneck elimination.","PeriodicalId":273746,"journal":{"name":"Proceedings. 1998 International Conference on Parallel Architectures and Compilation Techniques (Cat. No.98EX192)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-10-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123861228","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Exploiting fine- and coarse-grain parallelism in embedded programs","authors":"I. Karkowski, H. Corporaal","doi":"10.1109/PACT.1998.727152","DOIUrl":"https://doi.org/10.1109/PACT.1998.727152","url":null,"abstract":"Due to the technological advances, mapping of embedded applications onto single-chip multiprocessor systems becomes a feasible and very interesting option. What is needed is an environment that supports the designer in transforming an algorithmic specification into a suitable parallel implementation. In this paper we present the results of our experiments with one such an environment, which we developed within our laboratory. As opposed to the existing ones, our framework semi-automatically exploits different kinds of coarse and fine-grain parallelism from an embedded program written in ANSI C. It employs functional pipelining and data set partitioning simultaneously with source-to-source program transformations to obtain the most advantageous hierarchical parallelizations. This combination results in high speedups for all tested benchmarks.","PeriodicalId":273746,"journal":{"name":"Proceedings. 1998 International Conference on Parallel Architectures and Compilation Techniques (Cat. No.98EX192)","volume":"131 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-10-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124254799","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Instance-wise reaching definition analysis for recursive programs using context-free transductions","authors":"Albert Cohen, J. Collard","doi":"10.1109/PACT.1998.727269","DOIUrl":"https://doi.org/10.1109/PACT.1998.727269","url":null,"abstract":"Automatic parallelization of recursive programs is still an open problem today, lacking suitable and precise static analyses. We present a novel reaching definition framework based on context-free transductions. The technique achieves a global and precise description of the data flow and discovers important semantic properties of programs. Taking the example of a real-world non-derecursivable program, we show the need for a reaching definition analysis able to handle run-time instances of statements separately. A running example sketches our parallelization scheme, and presents our reaching definition analysis. Future fruitful research, at the crossroad of program analysis and formal language theory, is also hinted at.","PeriodicalId":273746,"journal":{"name":"Proceedings. 1998 International Conference on Parallel Architectures and Compilation Techniques (Cat. No.98EX192)","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-10-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122536153","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Michael Schmitt, Maximilian Ibel, A. Acharya, K. Schauser
{"title":"Adaptive receiver notification for non-dedicated workstation clusters","authors":"Michael Schmitt, Maximilian Ibel, A. Acharya, K. Schauser","doi":"10.1109/PACT.1998.727259","DOIUrl":"https://doi.org/10.1109/PACT.1998.727259","url":null,"abstract":"Efficient communication in a NOW environment can be a challenging task. Depending on the application, the architecture of the nodes and the characteristics of other processes running on the nodes, different communication strategies can be appropriate. In this paper, we evaluate an adaptive scheme which selects between multiple communication strategies depending on the current situation. We focus on strategies for receiver notification under varying load conditions. Previous research has shown that in a non-dedicated environment, spin-block strategies can avoid scheduling anomalies which can cause several orders of magnitude of performance degradation. However, research on these strategies has focused on a fixed spin-delay. Our scheme achieves better performance than static spin-block schemes on workstation clusters with varying load.","PeriodicalId":273746,"journal":{"name":"Proceedings. 1998 International Conference on Parallel Architectures and Compilation Techniques (Cat. No.98EX192)","volume":"236 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-10-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115999272","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Optimistic register coalescing","authors":"Jinpyo Park, Soo-Mook Moon","doi":"10.1109/PACT.1998.727246","DOIUrl":"https://doi.org/10.1109/PACT.1998.727246","url":null,"abstract":"Graph-coloring register allocators eliminate copies by coalescing the source and target node of a copy if they do not interfere in the interference graph. Coalescing is, however, known to be harmful to the colorability of the graph because it tends to yield a graph with nodes of higher degrees. Unlike aggressive coalescing which coalesces any pair of non-interfering copy-related nodes, conservative coalescing or iterated coalescing perform safe coalescing that preserves the colorability. Unfortunately, these heuristics give up coalescing too early, losing many opportunities of coalescing that would turn out to be safe. Moreover, they ignore the fact that coalescing may even improve the colorability of the graph by reducing the degree of neighbor nodes that are interfering with both the source and target nodes being coalesced. This paper proposes a new heuristic called optimistic coalescing which optimistically performs aggressive coalescing, thus fully exploiting the positive impact of coalescing, yet when a coalesced node is to be spilled, it is split back into separate nodes; there as a better chance of coloring one of them which reduces the overall spill cost.","PeriodicalId":273746,"journal":{"name":"Proceedings. 1998 International Conference on Parallel Architectures and Compilation Techniques (Cat. No.98EX192)","volume":"64 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-10-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122593517","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Improving compiler and run-time support for adaptive irregular codes","authors":"Hwansoo Han, C. Tseng","doi":"10.1109/PACT.1998.727289","DOIUrl":"https://doi.org/10.1109/PACT.1998.727289","url":null,"abstract":"Irregular reductions form the core of adaptive irregular codes. On distributed-memory multiprocessors, they are parallelized either using sophisticated run-time systems (e.g., CHAOS, PILAR) or the shared-memory interface supported by software DSMs (e.g., GYM, TreadMarks). We introduce LOCALWRITE, a new technique based on the owner-computes rule which eliminates the need for buffers or synchronized writes but may replicate computation. We evaluate its performance for irregular codes while varying connectivity, locality, and adaptivity. LOCALWRITE improves performance by 50-150% compared to using replicated buffers, and can match or exceed gather/scatter for applications with low locality or high adaptivity.","PeriodicalId":273746,"journal":{"name":"Proceedings. 1998 International Conference on Parallel Architectures and Compilation Techniques (Cat. No.98EX192)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-10-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125746475","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}