Proceedings. 1998 International Conference on Parallel Architectures and Compilation Techniques (Cat. No.98EX192)最新文献_第4页

Performance of message-passing systems using a zero-copy communication protocol 使用零拷贝通信协议的消息传递系统的性能

Proceedings. 1998 International Conference on Parallel Architectures and Compilation Techniques (Cat. No.98EX192) Pub Date : 1998-10-12 DOI: 10.1109/PACT.1998.727260

Panagiotis Melas, E. Zaluska

引用次数: 0

Dynamic elimination of pointer-expressions 动态消除指针表达式

Proceedings. 1998 International Conference on Parallel Architectures and Compilation Techniques (Cat. No.98EX192) Pub Date : 1998-10-12 DOI: 10.1109/PACT.1998.727185

Nitzan Weinberg, D. Nagle

引用次数: 8

Optical versus electronic bus for address-transactions in future SMP architectures 未来SMP架构中地址交易的光学与电子总线

Proceedings. 1998 International Conference on Parallel Architectures and Compilation Techniques (Cat. No.98EX192) Pub Date : 1998-10-12 DOI: 10.1109/PACT.1998.727137

W. Hlayhel, D. Litaize, L. Fesquet, J. Collet

引用次数: 9

Scanning polyhedra without Do-loops 扫描多面体没有Do-loops

Proceedings. 1998 International Conference on Parallel Architectures and Compilation Techniques (Cat. No.98EX192) Pub Date : 1998-10-12 DOI: 10.1109/PACT.1998.727127

Pierre Boulet, P. Feautrier

引用次数: 42

Load balancing in individual-based spatial applications 基于个体的空间应用程序中的负载平衡

Proceedings. 1998 International Conference on Parallel Architectures and Compilation Techniques (Cat. No.98EX192) Pub Date : 1998-10-12 DOI: 10.1109/PACT.1998.727273

Fehmina Merchant, L. Bic, M. Dillencourt

引用次数: 9

Origin 2000 design enhancements for communication intensive applications Origin 2000设计增强了通信密集型应用程序

Proceedings. 1998 International Conference on Parallel Architectures and Compilation Techniques (Cat. No.98EX192) Pub Date : 1998-10-12 DOI: 10.1109/PACT.1998.727141

Gheith A. Abandah, E. Davidson

引用次数: 6

Using algebraic transformations to optimize expression evaluation in scientific code 使用代数变换优化科学代码中的表达式计算

Proceedings. 1998 International Conference on Parallel Architectures and Compilation Techniques (Cat. No.98EX192) Pub Date : 1998-10-12 DOI: 10.1109/PACT.1998.727284

J. Zory, Fabien Coelho

{"title":"Using algebraic transformations to optimize expression evaluation in scientific code","authors":"J. Zory, Fabien Coelho","doi":"10.1109/PACT.1998.727284","DOIUrl":"https://doi.org/10.1109/PACT.1998.727284","url":null,"abstract":"Algebraic properties such as associativity or distributivity allow the manipulation of a set of mathematically equivalent expressions. However as shown in this paper the cost of evaluating such expressions on a computer is not constant within this domain. We suggest the use of algebraic transformations to improve the performance of computationally intensive applications on modern computer architectures. We claim that taking into account instruction-level parallelism and the new capabilities of processors when applying these transformations leads to large run-time improvements. Due to a combinatorial explosion, associative commutative pattern-matching techniques cannot systematically be used in this context. Thus, we introduce two performance enhancing algorithms providing factorization and multiply-add extraction heuristics and choice criteria based on a simple cost model. This paper describes our approach and a first implementation. Experiments on real code, including an excerpt from SPEC FP95, are very promising since we automatically obtain the same results as manual transformations, with a performance improvement by a factor of up to three.","PeriodicalId":273746,"journal":{"name":"Proceedings. 1998 International Conference on Parallel Architectures and Compilation Techniques (Cat. No.98EX192)","volume":"275 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-10-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133132514","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 24

Static methods in hybrid branch prediction 混合分支预测中的静态方法

Proceedings. 1998 International Conference on Parallel Architectures and Compilation Techniques (Cat. No.98EX192) Pub Date : 1998-10-12 DOI: 10.1109/PACT.1998.727254

D. Grunwald, Donald C. Lindsay, B. Zorn

{"title":"Static methods in hybrid branch prediction","authors":"D. Grunwald, Donald C. Lindsay, B. Zorn","doi":"10.1109/PACT.1998.727254","DOIUrl":"https://doi.org/10.1109/PACT.1998.727254","url":null,"abstract":"Hybrid branch predictors combine the predictions of multiple single-level or two-level branch predictors. The prediction-combining hardware-the \"meta-predictor\"-may itself be large, complex and slow. We show that the combination function is better performed statically, using prediction hints in the branch instructions. The hints are set by profiling or static analysis. Although the meta-predictor is static, the actual predictions remain dynamic, so there is little risk of worst-case performance. An important advantage of our approach is that a branch site only causes interference within a single component predictor reducing capacity demands. We argue that our proposal is implementable, and that it addresses the scaling issues currently facing hardware designers. We show that the static hybrid method we propose is more effective than existing techniques based on dynamic selection, and requires less hardware. For example, one result shows a conventional 4096-bit dynamic selection mechanism getting a 4.7% average miss rate, while our static approach gets 3.6%. These results are obtained with the Instruction Benchmark Suite (IBS), a realistic whole-system benchmark, and the SPECint95 suite, using realistic hardware sizes. All the results we present are based on a cross-validation methodology, in which the profile data used for static selection are based on training inputs that are entirely different from the inputs used to evaluate the performance of the technique.","PeriodicalId":273746,"journal":{"name":"Proceedings. 1998 International Conference on Parallel Architectures and Compilation Techniques (Cat. No.98EX192)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-10-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114938157","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 36

Sirocco: cost-effective fine-grain distributed shared memory Sirocco:高性价比的细粒度分布式共享内存

Proceedings. 1998 International Conference on Parallel Architectures and Compilation Techniques (Cat. No.98EX192) Pub Date : 1998-10-12 DOI: 10.1109/PACT.1998.727144

I. Schoinas, B. Falsafi, M. Hill, J. Larus, D. Wood

{"title":"Sirocco: cost-effective fine-grain distributed shared memory","authors":"I. Schoinas, B. Falsafi, M. Hill, J. Larus, D. Wood","doi":"10.1109/PACT.1998.727144","DOIUrl":"https://doi.org/10.1109/PACT.1998.727144","url":null,"abstract":"Software fine-grain distributed shared memory (FGDSM) provides a simplified shared-memory programming interface with minimal or no hardware support. Originally software FGDSMs targeted uniprocessor-node parallel machines. This paper presents Sirocco, a family of software FGDSMs implemented on a network of low-cost SMPs. Sirocco takes full advantage of SMP nodes by implementing inter-node sharing directly in hardware and overlapping computation with protocol execution. To maintain correct shared-memory semantics, however SMP nodes require mechanisms to guarantee atomic coherence operations. Multiple SMP processors may also result in contention for shared resources and reduce performance. SMP nodes also impact the cost trade-off. While SMPs typically charge higher price-premiums, for a given system size SMP nodes substantially reduce networking hardware requirement as compared to uniprocessor nodes. In this paper, we ask the question \"Are SMPs cost-effective building blocks for software FGDSM?\" We present experimental measurements on Sirocco implementations ranging from an all-software system to a system with minimal hardware support. Together with simple cost models we show that low-cost SMP nodes: (i) result in competitive performance with uniprocessor nodes, (ii) substantially reduce hardware requirement and are more cost-effective than uniprocessor nodes, (iii) significantly benefit from hardware support for coherence operations, and (iv) are especially beneficial for FGDSMs with high-overhead coherence operations.","PeriodicalId":273746,"journal":{"name":"Proceedings. 1998 International Conference on Parallel Architectures and Compilation Techniques (Cat. No.98EX192)","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-10-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129139393","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 32

A direct-execution framework for fast and accurate simulation of superscalar processors 一种用于快速精确模拟超标量处理器的直接执行框架

Proceedings. 1998 International Conference on Parallel Architectures and Compilation Techniques (Cat. No.98EX192) Pub Date : 1998-10-12 DOI: 10.1109/PACT.1998.727263

Venkata Krishnan, J. Torrellas

{"title":"A direct-execution framework for fast and accurate simulation of superscalar processors","authors":"Venkata Krishnan, J. Torrellas","doi":"10.1109/PACT.1998.727263","DOIUrl":"https://doi.org/10.1109/PACT.1998.727263","url":null,"abstract":"Multiprocessor system evaluation has traditionally been based on direct-execution based Execution-Driven Simulations (EDS). In such environments, the processor component of the system is not fully modeled. With wide issue superscalar processors being the norm in today's multiprocessor nodes, there is an urgent need for modeling the processor accurately. However, using direct execution to model a superscalar processor has been considered an open problem. Hence, current approaches model the processor by interpreting the application executable. Unfortunately, this approach can be slow. In this paper, we propose a novel direct-execution framework that allows accurate simulation of wide-issue superscalar processors without the need for code interpretation. This is achieved with the aid of an Interface Window between the front-end and the architectural simulator, that buffers the necessary information. This eliminates the need for full-fledged instruction emulation. Overall, this approach enables detailed yet fast EDS of superscalar processors. Finally, we evaluate the framework and show good performance for uni- and multiprocessor configurations.","PeriodicalId":273746,"journal":{"name":"Proceedings. 1998 International Conference on Parallel Architectures and Compilation Techniques (Cat. No.98EX192)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-10-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134440675","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 58