{"title":"Superscalar execution with dynamic data forwarding","authors":"S. Onder, Rajiv Gupta","doi":"10.1109/PACT.1998.727183","DOIUrl":"https://doi.org/10.1109/PACT.1998.727183","url":null,"abstract":"We empirically demonstrate that in order to take advantage of increasing issue widths, superscalar processors require quadratically growing instruction window sizes. Since conventional central window design aims to provide full data fan-out to all the instructions which are in the window, designing large instruction windows using conventional techniques is not feasible. We show that full data fan-out is not necessary for achieving high performance when a novel approach is used to distribute the values. We use direct matching using a small on chip memory called the wait memory to implement the instruction window and bring in a small subset of instructions which are likely to become ready into a match unit where instruction selection and operand matching tasks are performed. We show that the match unit needs to grow only linearly with the issue width. We use SPEC95 benchmarks to demonstrate that at a given instruction window size our algorithm provides over 90 percent of the IPC that can be obtained by a central window implementation that provides full data fan-out.","PeriodicalId":273746,"journal":{"name":"Proceedings. 1998 International Conference on Parallel Architectures and Compilation Techniques (Cat. No.98EX192)","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-10-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129263989","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
E. Özer, Sumedh W. Sathaye, Kishore N. Menezes, S. Banerjia, Matthew D. Jennings, T. Conte
{"title":"A fast interrupt handling scheme for VLIW processors","authors":"E. Özer, Sumedh W. Sathaye, Kishore N. Menezes, S. Banerjia, Matthew D. Jennings, T. Conte","doi":"10.1109/PACT.1998.727184","DOIUrl":"https://doi.org/10.1109/PACT.1998.727184","url":null,"abstract":"Interrupt handling in out-of-order execution processors requires complex hardware schemes to maintain the sequential state. The amount of hardware will be substantial in VLIW architectures due to the nature of issuing a very large number of instructions in each cycle. It is hard to implement precise interrupts in out-of-order execution machines, especially in VLIW processors. In this paper, we will apply the reorder buffer with future file and the history buffer methods to a VLIW platform, and present a novel scheme, called the current-state buffer, which employs modest hardware with compiler support. Unlike the other interrupt handling schemes, the current-state buffer does not keep history state, result buffering or bypass mechanisms. It is a fast interrupt handling scheme with a relatively small buffer that records the execution and exception status of operations. It is suitable for embedded processors that require a fast interrupt handling mechanism with modest hardware.","PeriodicalId":273746,"journal":{"name":"Proceedings. 1998 International Conference on Parallel Architectures and Compilation Techniques (Cat. No.98EX192)","volume":"49 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-10-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126272963","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
M. Kandemir, A. Choudhary, J. Ramanujam, P. Banerjee
{"title":"A matrix-based approach to the global locality optimization problem","authors":"M. Kandemir, A. Choudhary, J. Ramanujam, P. Banerjee","doi":"10.1109/PACT.1998.727266","DOIUrl":"https://doi.org/10.1109/PACT.1998.727266","url":null,"abstract":"Global locality analysis is a technique for improving the cache performance of a sequence of loop nests through a combination of loop and data layout optimizations. Pure loop transformations are restricted by data dependences and may not be very successful in optimizing imperfectly nested loops; the impact of a data transformation on an array might be program-wide. Therefore, in this paper we argue for a combined approach which employs both loop and data transformations. The method enjoys the advantages of the most of the previous techniques for enhancing locality and is efficient. In our approach, the loop nests are processed one by one and the data layout constraints obtained from one nest are propagated for optimization of the remaining loop nests. We show that this process can be put in a simple matrix framework which can be manipulated by an optimizing compiler. The search space that we consider for possible loop transformations comprises general non-singular linear transformation matrices and the data layouts that we consider are those which can be expressed using hyperplanes. Experiments using several programs on an SGI Origin 2000 distributed-shared-memory machine demonstrate the efficacy of our approach.","PeriodicalId":273746,"journal":{"name":"Proceedings. 1998 International Conference on Parallel Architectures and Compilation Techniques (Cat. No.98EX192)","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-10-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115934236","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Handling cross interferences by cyclic cache line coloring","authors":"Daniela Genius","doi":"10.1109/PACT.1998.727180","DOIUrl":"https://doi.org/10.1109/PACT.1998.727180","url":null,"abstract":"Cross interference, conflicting data from several arrays, is particularly grave for caches with limited associativity. We present a uniform scheme that reduces both self and cross interference. Techniques for cyclic register allocation, namely the meeting graph, help to improve the usage of cache lines and to avoid conflicts. Cyclic graph coloring determines a new memory mapping function. Preliminary experiments show that in spite of the penalty for the more complex indexing functions, run times are improved.","PeriodicalId":273746,"journal":{"name":"Proceedings. 1998 International Conference on Parallel Architectures and Compilation Techniques (Cat. No.98EX192)","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-10-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133972940","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
François Galilée, Jean-Louis Roch, G. H. Cavalheiro, M. Doreille
{"title":"Athapascan-1: On-line building data flow graph in a parallel language","authors":"François Galilée, Jean-Louis Roch, G. H. Cavalheiro, M. Doreille","doi":"10.1109/PACT.1998.727176","DOIUrl":"https://doi.org/10.1109/PACT.1998.727176","url":null,"abstract":"In order to achieve practical efficient execution on a parallel architecture, a knowledge of the data dependencies related to the application appears as the key point for building an efficient schedule. By restricting accesses in shared memory, we show that such a data dependency graph can be computed on-line on a distributed architecture. The overhead introduced is bounded with respect to the parallelism expressed by the user: each basic computation corresponds to a user-defined task, each data-dependency to a user-defined data structure. We introduce a language named Athapascan-1 that allows to build a graph of dependencies from a strong typing of shared memory accesses. We detail compilation and implementation of the language. Besides, the performance of a code (parallel time, communication and arithmetic works, memory space) are defined from a cost model without the need of a machine model. We exhibit efficient scheduling with respect to these costs on theoretical machine models.","PeriodicalId":273746,"journal":{"name":"Proceedings. 1998 International Conference on Parallel Architectures and Compilation Techniques (Cat. No.98EX192)","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-10-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122142108","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Transformations for improving data access locality in non-perfectly nested loops","authors":"D. Kulkarni","doi":"10.1109/PACT.1998.727267","DOIUrl":"https://doi.org/10.1109/PACT.1998.727267","url":null,"abstract":"Loop transformation techniques have matured to the point where the techniques are well integrated into production optimizing compilers. However, we believe that new and aggressive techniques are necessary because: i) computer system manufacturers have announced their plans for forthcoming processors with over 1 GHz clock frequency, wherein the miss penalties can be very high, and ii) transformation techniques have saturated in that they have delivered majority of the benefit that can be obtained with perfectly nested loops. The new techniques must target improvement of coverage, that is the classes of loops that can be optimized for locality of data access. In this paper, we present a new technique called size-reduction transformation to improve data access locality in a class of nonperfectly nested loops. The new technique is very effective when existing techniques, namely, linear loop and array transformations, fail to improve locality of reference. Size-reduction transformations are implemented in IBM's Fortran 90 optimizing compiler released recently, and have contributed significantly to the high performance of the compiler.","PeriodicalId":273746,"journal":{"name":"Proceedings. 1998 International Conference on Parallel Architectures and Compilation Techniques (Cat. No.98EX192)","volume":"52 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-10-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115089288","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A multithreaded runtime environment with thread migration for a HPF data-parallel compiler","authors":"L. Bougé, P. Hatcher, R. Namyst, Christian Pérez","doi":"10.1109/PACT.1998.727301","DOIUrl":"https://doi.org/10.1109/PACT.1998.727301","url":null,"abstract":"This paper studies the benefits of compiling data-parallel languages onto a multithreaded runtime environment providing dynamic thread migration facilities. Each abstract process is mapped onto a thread, so that dynamic load balancing can be achieved by migrating threads among the processing nodes. We describe and evaluate an implementation of this idea in the adaptor HPF compiler. We show that no deep modification of the compiler are needed, and that the overhead of managing threads can be kept small. As an experimental validation, we report on an HPF implementation of the Gauss partial pivoting algorithm. We show that using an initial BLOCK data distribution with our dynamic load balancing scheme can reach the performance of the optimal cyclic distribution.","PeriodicalId":273746,"journal":{"name":"Proceedings. 1998 International Conference on Parallel Architectures and Compilation Techniques (Cat. No.98EX192)","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-10-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115470943","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Design study of shared memory in VLIW video signal processors","authors":"Z. Wu, W. Wolf","doi":"10.1109/PACT.1998.727148","DOIUrl":"https://doi.org/10.1109/PACT.1998.727148","url":null,"abstract":"Programmable video signal processors (VSPs) play an important role in multimedia applications due to their high performance and flexibility. In order to exploit the huge amount of parallelism inherent in the applications, VSPs employ aggressive parallel architectures, among which Very Long Instruction Word (VLIW) is becoming increasingly popular. For video signal processing a carefully designed memory system is of particular importance, as video-rate applications have generated an unusual demand for high-bandwidth and low-latency memory access. Although many papers have addressed this issue for systems consisting of general-purpose microprocessors, few of them have considered environments containing VSPs, especially those based on VLIW VSPs. In this paper, we outline the problems involved in this specific context and compare five memory architectures for shared memory based VSPs. Our simulation results of six video applications show that combining caches with stream buffers in the proper way provides the highest performance.","PeriodicalId":273746,"journal":{"name":"Proceedings. 1998 International Conference on Parallel Architectures and Compilation Techniques (Cat. No.98EX192)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-10-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117126924","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
S. Goto, A. Kubota, Toshihiko Tanaka, M. Goshima, S. Mori, H. Nakashima, S. Tomita
{"title":"Optimized code generation for heterogeneous computing environment using parallelizing compiler TINPAR","authors":"S. Goto, A. Kubota, Toshihiko Tanaka, M. Goshima, S. Mori, H. Nakashima, S. Tomita","doi":"10.1109/PACT.1998.727305","DOIUrl":"https://doi.org/10.1109/PACT.1998.727305","url":null,"abstract":"This paper presents a compiling technique to generate optimized codes for heterogeneous computing environment. This paper also proposes a new dynamic load redistribution mechanism which can adaptively and dynamically distribute tasks among computers according to their available computing power which may vary during the computation. As the results of the performance evaluation, we could confirm that the generated codes are effectively executed in a heterogeneous computing environment with dynamic load change.","PeriodicalId":273746,"journal":{"name":"Proceedings. 1998 International Conference on Parallel Architectures and Compilation Techniques (Cat. No.98EX192)","volume":"61 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-10-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121880730","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Integrating loop and data transformations for global optimisation","authors":"M. O’Boyle, P. Knijnenburg","doi":"10.1109/PACT.1998.727131","DOIUrl":"https://doi.org/10.1109/PACT.1998.727131","url":null,"abstract":"This paper is concerned with integrating global data transformations and local loop transformations in order to minimise overhead on distributed shared memory machines such as the SGi Origin 2000. By first developing an extended algebraic transformation framework, a new technique to allow the static application of global data transformations, such as partitioning, to reshaped arrays is presented, eliminating the need for expensive temporary copies and hence eliminating any communication and synchronisation. In addition, by integrating loop and data transformations, any introduced poor spatial locality and expensive array subscripts can be eliminated. A specific optimisation algorithm is derived and applied to well-known benchmarks, where it is shown to give a significant improvement in execution time over existing approaches.","PeriodicalId":273746,"journal":{"name":"Proceedings. 1998 International Conference on Parallel Architectures and Compilation Techniques (Cat. No.98EX192)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-10-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125967914","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}