Handling cross interferences by cyclic cache line coloring

Abstract

Cross interference, conflicting data from several arrays, is particularly grave for caches with limited associativity. We present a uniform scheme that reduces both self and cross interference. Techniques for cyclic register allocation, namely the meeting graph, help to improve the usage of cache lines and to avoid conflicts. Cyclic graph coloring determines a new memory mapping function. Preliminary experiments show that in spite of the penalty for the more complex indexing functions, run times are improved.