发布求助
文献互助 智能选刊 最新文献

2011 IEEE 9th International New Circuits and systems conference最新文献

筛选
英文 中文
A low power VLSI implementation of the Izhikevich neuron model Izhikevich神经元模型的低功耗VLSI实现
2011 IEEE 9th International New Circuits and systems conference Pub Date : 2011-06-26 DOI: 10.1109/NEWCAS.2011.5981282
A. S. Demirkol, S. Ozoguz
{"title":"A low power VLSI implementation of the Izhikevich neuron model","authors":"A. S. Demirkol, S. Ozoguz","doi":"10.1109/NEWCAS.2011.5981282","DOIUrl":"https://doi.org/10.1109/NEWCAS.2011.5981282","url":null,"abstract":"We present a low-power VLSI implementation of the Izhikevich neuron model utilizing two first-order log-domain filters as the main building block. One of the filters includes an active diode connection in order to lower current levels to obtain a low-power, large time constant design. Thus, the neuron circuit operates in sub-threshold regime with biological time scale. The possible applications of the presented implementation are simulating large scale VLSI neural networks and building hybrid interface systems. The simulation results demonstrate the success of replicating the firing patterns of real neurons.","PeriodicalId":271676,"journal":{"name":"2011 IEEE 9th International New Circuits and systems conference","volume":"275 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-06-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115883642","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 20
The design and assessment of a secure passive RFID sensor system 安全无源RFID传感器系统的设计与评估
2011 IEEE 9th International New Circuits and systems conference Pub Date : 2011-06-26 DOI: 10.1109/NEWCAS.2011.5981327
M. Todd, W. Burleson, R. Tessier
{"title":"The design and assessment of a secure passive RFID sensor system","authors":"M. Todd, W. Burleson, R. Tessier","doi":"10.1109/NEWCAS.2011.5981327","DOIUrl":"https://doi.org/10.1109/NEWCAS.2011.5981327","url":null,"abstract":"This paper presents a low-overhead security enhancement for EPC Class-1 Generation-2 (Gen2) compatible RFID tags that provides data confidentiality for a series of common threats. The new security circuit, based on the PRESENT block cipher, is fully integrated into a passive RFID tag architecture. The circuit is evaluated in an FPGA-based emulation platform which allows for the validation of the circuit and the use of a protocol which seamlessly interacts with a standard off-the-shelf RFID reader. A complete system, including a temperature sensor attached to the emulated tag, was successfully tested in the lab using an existing Gen2 RFID reader. The hardware overhead of the security enhancement is roughly 1,900 logic gates.","PeriodicalId":271676,"journal":{"name":"2011 IEEE 9th International New Circuits and systems conference","volume":"202 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-06-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116218852","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
A phase error calibration DLL with edge combiner for wide-range operation 带边缘组合器的相位误差校准DLL，适用于大范围操作
2011 IEEE 9th International New Circuits and systems conference Pub Date : 2011-06-26 DOI: 10.1109/NEWCAS.2011.5981204
Po-Chun Huang, Chi-Jih Shih, Yu-Chang Tsai, Kuo-Hsing Cheng
{"title":"A phase error calibration DLL with edge combiner for wide-range operation","authors":"Po-Chun Huang, Chi-Jih Shih, Yu-Chang Tsai, Kuo-Hsing Cheng","doi":"10.1109/NEWCAS.2011.5981204","DOIUrl":"https://doi.org/10.1109/NEWCAS.2011.5981204","url":null,"abstract":"In this paper, a technique to reduce the output jitter and the wide-range operation is presented. A wide-range voltage controlled delay line (WRVCDL) uses multi-band to operate on wide-range. The proposed DLL operates from 25MHz to 250MHz. An edge combiner (EC) is used to increase the output frequency range. It synthesizes frequencies from 250MHz to 2.5GHz. The output of EC will be a 50% cycle in all different frequencies. The presented clock generator uses a dynamical phase detector (DPD) to effectively reduce the DLL output jitter from 7.81ps to 5.4ps at 250MHz. In simulation results which show the output jitter is from 16.2p to 11.7p at 2.5GHz by using the calibration. The static phase error of the proposed DLL reduced from 7.35ps to 2.1ps at 250MHz. The proposed DLL has been fabricated in 0.18μm 1P6M CMOS process. The total power consumption is 6.14mW in 2.5GHz with buffer and the core area is 0.033mm2.","PeriodicalId":271676,"journal":{"name":"2011 IEEE 9th International New Circuits and systems conference","volume":"2006 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-06-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125836290","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
Novel high speed differential CMOS flip-flop for ultra low-voltage appications 用于超低电压应用的新型高速差分CMOS触发器
2011 IEEE 9th International New Circuits and systems conference Pub Date : 2011-06-26 DOI: 10.1109/NEWCAS.2011.5981300
Y. Berg
{"title":"Novel high speed differential CMOS flip-flop for ultra low-voltage appications","authors":"Y. Berg","doi":"10.1109/NEWCAS.2011.5981300","DOIUrl":"https://doi.org/10.1109/NEWCAS.2011.5981300","url":null,"abstract":"In this paper we present a novel ultra-low-voltage (ULV) CMOS flip-flop. The ULV flip-flop offers increased speed compared to other FF's for low supply voltages. The pulse generator (PG) circuit in a conventional sense amplifier SAFF is replaced by a high-speed tristate edge generator (EG) with a rise- and fall-time less than 1/10 of an inverter operating with the same supply voltage. In essence the delay of the ultra-low-voltage FF (UFF) presented in this paper is located in the latch stage. In terms of maximum operating frequency for ULV operation the UFF may be used at frequencies 10 times compared to more conventional FF's. The power-delay-product (PDP) of the UFF is significantly reduced accordingly. The simulated data presented is obtained using the Spectre simulator provided by Cadence and valid for a 90nm TMC CMOS process with inherent threshold voltages of 250mV. The transistors used for the low voltage FF are minimum sized.","PeriodicalId":271676,"journal":{"name":"2011 IEEE 9th International New Circuits and systems conference","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-06-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127083045","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
A dependable power grid optimization algorithm considering NBTI timing degradation 考虑NBTI时序退化的可靠电网优化算法
2011 IEEE 9th International New Circuits and systems conference Pub Date : 2011-06-26 DOI: 10.1109/NEWCAS.2011.5981247
M. Fukui, Syota Nakai, H. Miki, S. Tsukiyama
{"title":"A dependable power grid optimization algorithm considering NBTI timing degradation","authors":"M. Fukui, Syota Nakai, H. Miki, S. Tsukiyama","doi":"10.1109/NEWCAS.2011.5981247","DOIUrl":"https://doi.org/10.1109/NEWCAS.2011.5981247","url":null,"abstract":"Reliability becomes one of the most important issues for designing LSIs. Negative bias temperature instability (NBTI) is a phenomenon in which performance of transistors deteriorates depending on temperature and transistor switching frequency. In the manufacturing process generations of 32 nm and 22 nm, it will be expected that timing degradation by NBTI becomes non-ignorable. This research proposes the high reliable power grid optimization technique in which timing degradation by NTBI of after-manufacture five or ten years was taken into consideration.","PeriodicalId":271676,"journal":{"name":"2011 IEEE 9th International New Circuits and systems conference","volume":"57 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-06-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130983293","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
Side-channel watermarks for embedded software 嵌入式软件的边信道水印
2011 IEEE 9th International New Circuits and systems conference Pub Date : 2011-06-26 DOI: 10.1109/NEWCAS.2011.5981323
G. Becker, W. Burleson, C. Paar
{"title":"Side-channel watermarks for embedded software","authors":"G. Becker, W. Burleson, C. Paar","doi":"10.1109/NEWCAS.2011.5981323","DOIUrl":"https://doi.org/10.1109/NEWCAS.2011.5981323","url":null,"abstract":"In this paper we introduce a new software watermarking mechanism for the embedded environment. The newly proposed software watermarking mechanism can be added at the assembly level and hides the watermark in the power consumption of the device. By using side-channel analysis techniques, the verifier can reliably detect his watermark in the power traces of the device. This new approach is especially well suited for embedded microcontrollers that have program memory protection. In comparison to other software watermark mechanisms a verifier does not need to have access to the software code or data memory to detect the watermark. This makes the detection of the watermarks very efficient for embedded applications in which access to the program code or data memory is very restricted. Our watermark method can therefore serve as a very easy and cost efficient way to detect software theft for embedded applications.","PeriodicalId":271676,"journal":{"name":"2011 IEEE 9th International New Circuits and systems conference","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-06-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130215427","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 13
Level-crossing based QAM demodulation for low-cost analog/RF testing 基于平交的QAM解调低成本模拟/射频测试
2011 IEEE 9th International New Circuits and systems conference Pub Date : 2011-06-26 DOI: 10.1109/NEWCAS.2011.5981317
N. Pous, F. Azais, L. Latorre, G. Confais, J. Rivoir
{"title":"Level-crossing based QAM demodulation for low-cost analog/RF testing","authors":"N. Pous, F. Azais, L. Latorre, G. Confais, J. Rivoir","doi":"10.1109/NEWCAS.2011.5981317","DOIUrl":"https://doi.org/10.1109/NEWCAS.2011.5981317","url":null,"abstract":"This paper concerns production test of analog and RF communication devices. The use of standard digital tester channel for the acquisition of modulated analog/RF signals is investigated in order to implement low-cost functional test. The idea is to use the comparator available in a standard digital test resource to record level-crossing events on a signal coming from the device under test, and then to apply a dedicated algorithm to retrieve the signal information. The proposed method is evaluated through both simulation and hardware experiments using the popular QAM coding scheme that combines both amplitude and phase shift-keying. The approach is generic and can be applied to a broad range of modulation schemes.","PeriodicalId":271676,"journal":{"name":"2011 IEEE 9th International New Circuits and systems conference","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-06-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130252515","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
CMOS low power current source with reduced circuit complexity 降低电路复杂度的CMOS低功率电流源
2011 IEEE 9th International New Circuits and systems conference Pub Date : 2011-06-26 DOI: 10.1109/NEWCAS.2011.5981208
A. Kasemaa, T. Rang, P. Annus
{"title":"CMOS low power current source with reduced circuit complexity","authors":"A. Kasemaa, T. Rang, P. Annus","doi":"10.1109/NEWCAS.2011.5981208","DOIUrl":"https://doi.org/10.1109/NEWCAS.2011.5981208","url":null,"abstract":"The paper describes the efficient CMOS technology based current source for system identification and it's layout realization with reduced circuit complexity. Square wave excitation current is preferred in energy constrained and embedded environment. It has been shown that by shortening the square waves, spectral purity of the excitation signals can be drastically improved. Further improvement can be achieved by introducing limited number of additional equally spaced current levels. The basic idea of such a solution is that by suitably adding several simple shortened pulses together some of the high energy harmonics are either further reduced or eliminated. This multilevel signal can be easily generated digitally and it enables simpler digital processing involving only additions and shifting. On the other hand required extra circuitry for multiple current levels should not eliminate main advantages of square wave excitation, such as reduced complexity and low consumption. Proposed solution improves the power consumption and reduces the complexity of the system as a whole compared to more generic approach. The current source output will be the shortened multilevel square wave signal. The output current value can be selected from range from 5 to 100 μA. The main advantage of this method is greater efficiency because for measuring cycle only one or two pairs of switchable current mirrors will be activated to drive the H-bridge.","PeriodicalId":271676,"journal":{"name":"2011 IEEE 9th International New Circuits and systems conference","volume":"104 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-06-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134046344","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
An analog core computing the center of pressure in a knee replacement prosthesis 膝关节置换术中计算压力中心的模拟核心
2011 IEEE 9th International New Circuits and systems conference Pub Date : 2011-06-26 DOI: 10.1109/NEWCAS.2011.5981230
C. Lahuec, M. Arzel
{"title":"An analog core computing the center of pressure in a knee replacement prosthesis","authors":"C. Lahuec, M. Arzel","doi":"10.1109/NEWCAS.2011.5981230","DOIUrl":"https://doi.org/10.1109/NEWCAS.2011.5981230","url":null,"abstract":"Predicting the lifespan of a knee prosthesis can be done by computing the force distribution, represented by the center of pressure (COP), onto the tibial part of the implant. The COP can be computed in-vivo by means of a telemetry system. The feasibility of such a telemetry system has been shown using a digital computing core. Both the complexity and the power consumption can be reduced using an analog computing core to compute the COP. The core is 10 times smaller than its digital counterpart and one oscillator is removed. Furthermore, only the value of the computed COP needs to be converted into digital. These result in a reduced power consumption of 5.5 percent. The current-mode computing core has been designed and simulated for a 0.35μm CMOS process.","PeriodicalId":271676,"journal":{"name":"2011 IEEE 9th International New Circuits and systems conference","volume":"416 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-06-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115995322","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
New V-band MHMIC six-port architecture 新的v波段MHMIC六端口架构
2011 IEEE 9th International New Circuits and systems conference Pub Date : 2011-06-26 DOI: 10.1109/NEWCAS.2011.5981260
D. Hammou, N. Hakem, N. Kandil, E. Moldovan, S. Tatu
{"title":"New V-band MHMIC six-port architecture","authors":"D. Hammou, N. Hakem, N. Kandil, E. Moldovan, S. Tatu","doi":"10.1109/NEWCAS.2011.5981260","DOIUrl":"https://doi.org/10.1109/NEWCAS.2011.5981260","url":null,"abstract":"This paper presents a new V-band MHMIC six-port architecture built on thin alumina substrate. This circuit is implemented using three 90° hybrid couplers and a new ring power divider. The S parameter measurements of the new ring power divider show wideband performances and high coupled-port phase and amplitude balance in the 57–64 GHz frequency band. The proposed six-port exhibits good phase and amplitude balance, while maintaining a good return loss. The proposed circuits are suitable for unlicensed indoor V-band high data-rate communications systems according to FCC standard.","PeriodicalId":271676,"journal":{"name":"2011 IEEE 9th International New Circuits and systems conference","volume":"119 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-06-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126904508","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
首页 上一页
0
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
提示
您的信息不完整，为了账户安全，请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
现在去查看 取消
×
提示
确定
请完成安全验证×
相关产品
×
本文献相关产品
联系我们：info@booksci.cn Book学术提供免费学术资源搜索服务，方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。 Copyright © 2023 布克学术 All rights reserved.
京ICP备2023020795号-1
ghs 京公网安备 11010802042870号
Book学术文献互助
Book学术文献互助群
群 号：604180095
Book学术官方微信
小红书