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2011 IEEE 9th International New Circuits and systems conference最新文献

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New V-band MHMIC six-port architecture 新的v波段MHMIC六端口架构
2011 IEEE 9th International New Circuits and systems conference Pub Date : 2011-06-26 DOI: 10.1109/NEWCAS.2011.5981260
D. Hammou, N. Hakem, N. Kandil, E. Moldovan, S. Tatu
{"title":"New V-band MHMIC six-port architecture","authors":"D. Hammou, N. Hakem, N. Kandil, E. Moldovan, S. Tatu","doi":"10.1109/NEWCAS.2011.5981260","DOIUrl":"https://doi.org/10.1109/NEWCAS.2011.5981260","url":null,"abstract":"This paper presents a new V-band MHMIC six-port architecture built on thin alumina substrate. This circuit is implemented using three 90° hybrid couplers and a new ring power divider. The S parameter measurements of the new ring power divider show wideband performances and high coupled-port phase and amplitude balance in the 57–64 GHz frequency band. The proposed six-port exhibits good phase and amplitude balance, while maintaining a good return loss. The proposed circuits are suitable for unlicensed indoor V-band high data-rate communications systems according to FCC standard.","PeriodicalId":271676,"journal":{"name":"2011 IEEE 9th International New Circuits and systems conference","volume":"119 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-06-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126904508","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
An analog core computing the center of pressure in a knee replacement prosthesis 膝关节置换术中计算压力中心的模拟核心
2011 IEEE 9th International New Circuits and systems conference Pub Date : 2011-06-26 DOI: 10.1109/NEWCAS.2011.5981230
C. Lahuec, M. Arzel
{"title":"An analog core computing the center of pressure in a knee replacement prosthesis","authors":"C. Lahuec, M. Arzel","doi":"10.1109/NEWCAS.2011.5981230","DOIUrl":"https://doi.org/10.1109/NEWCAS.2011.5981230","url":null,"abstract":"Predicting the lifespan of a knee prosthesis can be done by computing the force distribution, represented by the center of pressure (COP), onto the tibial part of the implant. The COP can be computed in-vivo by means of a telemetry system. The feasibility of such a telemetry system has been shown using a digital computing core. Both the complexity and the power consumption can be reduced using an analog computing core to compute the COP. The core is 10 times smaller than its digital counterpart and one oscillator is removed. Furthermore, only the value of the computed COP needs to be converted into digital. These result in a reduced power consumption of 5.5 percent. The current-mode computing core has been designed and simulated for a 0.35μm CMOS process.","PeriodicalId":271676,"journal":{"name":"2011 IEEE 9th International New Circuits and systems conference","volume":"416 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-06-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115995322","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
The design and assessment of a secure passive RFID sensor system 安全无源RFID传感器系统的设计与评估
2011 IEEE 9th International New Circuits and systems conference Pub Date : 2011-06-26 DOI: 10.1109/NEWCAS.2011.5981327
M. Todd, W. Burleson, R. Tessier
{"title":"The design and assessment of a secure passive RFID sensor system","authors":"M. Todd, W. Burleson, R. Tessier","doi":"10.1109/NEWCAS.2011.5981327","DOIUrl":"https://doi.org/10.1109/NEWCAS.2011.5981327","url":null,"abstract":"This paper presents a low-overhead security enhancement for EPC Class-1 Generation-2 (Gen2) compatible RFID tags that provides data confidentiality for a series of common threats. The new security circuit, based on the PRESENT block cipher, is fully integrated into a passive RFID tag architecture. The circuit is evaluated in an FPGA-based emulation platform which allows for the validation of the circuit and the use of a protocol which seamlessly interacts with a standard off-the-shelf RFID reader. A complete system, including a temperature sensor attached to the emulated tag, was successfully tested in the lab using an existing Gen2 RFID reader. The hardware overhead of the security enhancement is roughly 1,900 logic gates.","PeriodicalId":271676,"journal":{"name":"2011 IEEE 9th International New Circuits and systems conference","volume":"202 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-06-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116218852","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Power supply noise and ground bounce aware pattern generation for delay testing 用于延迟测试的电源噪声和地面反弹感知模式生成
2011 IEEE 9th International New Circuits and systems conference Pub Date : 2011-06-26 DOI: 10.1109/NEWCAS.2011.5981222
Aida Todri-Sanial, A. Bosio, L. Dilillo, P. Girard, S. Pravossoudovitch, A. Virazel
{"title":"Power supply noise and ground bounce aware pattern generation for delay testing","authors":"Aida Todri-Sanial, A. Bosio, L. Dilillo, P. Girard, S. Pravossoudovitch, A. Virazel","doi":"10.1109/NEWCAS.2011.5981222","DOIUrl":"https://doi.org/10.1109/NEWCAS.2011.5981222","url":null,"abstract":"Power supply noise and ground bounce can significantly impact the circuit's performance. Existing delay testing techniques do not capture the impact of combined and uncorrelated power supply noise and ground bounce for critical path delay analysis. They capture the worst case power supply noise in order to obtain the worst case path delay. We show that such assumption is not necessarily sufficient and combined effects of both power and ground noise should be considered for path delay analysis. First, we propose accurate close-form mathematical models for capturing the path delay variations in the presence of power supply noise and ground bounce. We utilize these models as the fitness function for pattern generation technique which is a simulated annealing based iterative process. In our experiments, we show that path delay variation can be significant if test patterns are not properly selected.","PeriodicalId":271676,"journal":{"name":"2011 IEEE 9th International New Circuits and systems conference","volume":"191 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-06-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116529955","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
Side-channel watermarks for embedded software 嵌入式软件的边信道水印
2011 IEEE 9th International New Circuits and systems conference Pub Date : 2011-06-26 DOI: 10.1109/NEWCAS.2011.5981323
G. Becker, W. Burleson, C. Paar
{"title":"Side-channel watermarks for embedded software","authors":"G. Becker, W. Burleson, C. Paar","doi":"10.1109/NEWCAS.2011.5981323","DOIUrl":"https://doi.org/10.1109/NEWCAS.2011.5981323","url":null,"abstract":"In this paper we introduce a new software watermarking mechanism for the embedded environment. The newly proposed software watermarking mechanism can be added at the assembly level and hides the watermark in the power consumption of the device. By using side-channel analysis techniques, the verifier can reliably detect his watermark in the power traces of the device. This new approach is especially well suited for embedded microcontrollers that have program memory protection. In comparison to other software watermark mechanisms a verifier does not need to have access to the software code or data memory to detect the watermark. This makes the detection of the watermarks very efficient for embedded applications in which access to the program code or data memory is very restricted. Our watermark method can therefore serve as a very easy and cost efficient way to detect software theft for embedded applications.","PeriodicalId":271676,"journal":{"name":"2011 IEEE 9th International New Circuits and systems conference","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-06-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130215427","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 13
Level-crossing based QAM demodulation for low-cost analog/RF testing 基于平交的QAM解调低成本模拟/射频测试
2011 IEEE 9th International New Circuits and systems conference Pub Date : 2011-06-26 DOI: 10.1109/NEWCAS.2011.5981317
N. Pous, F. Azais, L. Latorre, G. Confais, J. Rivoir
{"title":"Level-crossing based QAM demodulation for low-cost analog/RF testing","authors":"N. Pous, F. Azais, L. Latorre, G. Confais, J. Rivoir","doi":"10.1109/NEWCAS.2011.5981317","DOIUrl":"https://doi.org/10.1109/NEWCAS.2011.5981317","url":null,"abstract":"This paper concerns production test of analog and RF communication devices. The use of standard digital tester channel for the acquisition of modulated analog/RF signals is investigated in order to implement low-cost functional test. The idea is to use the comparator available in a standard digital test resource to record level-crossing events on a signal coming from the device under test, and then to apply a dedicated algorithm to retrieve the signal information. The proposed method is evaluated through both simulation and hardware experiments using the popular QAM coding scheme that combines both amplitude and phase shift-keying. The approach is generic and can be applied to a broad range of modulation schemes.","PeriodicalId":271676,"journal":{"name":"2011 IEEE 9th International New Circuits and systems conference","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-06-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130252515","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
A dependable power grid optimization algorithm considering NBTI timing degradation 考虑NBTI时序退化的可靠电网优化算法
2011 IEEE 9th International New Circuits and systems conference Pub Date : 2011-06-26 DOI: 10.1109/NEWCAS.2011.5981247
M. Fukui, Syota Nakai, H. Miki, S. Tsukiyama
{"title":"A dependable power grid optimization algorithm considering NBTI timing degradation","authors":"M. Fukui, Syota Nakai, H. Miki, S. Tsukiyama","doi":"10.1109/NEWCAS.2011.5981247","DOIUrl":"https://doi.org/10.1109/NEWCAS.2011.5981247","url":null,"abstract":"Reliability becomes one of the most important issues for designing LSIs. Negative bias temperature instability (NBTI) is a phenomenon in which performance of transistors deteriorates depending on temperature and transistor switching frequency. In the manufacturing process generations of 32 nm and 22 nm, it will be expected that timing degradation by NBTI becomes non-ignorable. This research proposes the high reliable power grid optimization technique in which timing degradation by NTBI of after-manufacture five or ten years was taken into consideration.","PeriodicalId":271676,"journal":{"name":"2011 IEEE 9th International New Circuits and systems conference","volume":"57 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-06-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130983293","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
Model order reduction for nonlinear macromodeling of RF circuits 射频电路非线性宏建模的模型降阶方法
2011 IEEE 9th International New Circuits and systems conference Pub Date : 2011-06-26 DOI: 10.1109/NEWCAS.2011.5981294
Marwan Kanaan, R. Khazaka
{"title":"Model order reduction for nonlinear macromodeling of RF circuits","authors":"Marwan Kanaan, R. Khazaka","doi":"10.1109/NEWCAS.2011.5981294","DOIUrl":"https://doi.org/10.1109/NEWCAS.2011.5981294","url":null,"abstract":"The simulation of Radio Frequency circuits can be very CPU expensive due to the large number of equations present as well as the density of the Jacobian matrix. This problem becomes even more pronounced when simulating a system containing multiple circuits. In this paper a model order reduction method is proposed for obtaining a reduced order nonlinear macromodel for an RF circuit block. This macromodel can then be efficiently used in an overall system simulation.","PeriodicalId":271676,"journal":{"name":"2011 IEEE 9th International New Circuits and systems conference","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-06-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124573699","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
CMOS low power current source with reduced circuit complexity 降低电路复杂度的CMOS低功率电流源
2011 IEEE 9th International New Circuits and systems conference Pub Date : 2011-06-26 DOI: 10.1109/NEWCAS.2011.5981208
A. Kasemaa, T. Rang, P. Annus
{"title":"CMOS low power current source with reduced circuit complexity","authors":"A. Kasemaa, T. Rang, P. Annus","doi":"10.1109/NEWCAS.2011.5981208","DOIUrl":"https://doi.org/10.1109/NEWCAS.2011.5981208","url":null,"abstract":"The paper describes the efficient CMOS technology based current source for system identification and it's layout realization with reduced circuit complexity. Square wave excitation current is preferred in energy constrained and embedded environment. It has been shown that by shortening the square waves, spectral purity of the excitation signals can be drastically improved. Further improvement can be achieved by introducing limited number of additional equally spaced current levels. The basic idea of such a solution is that by suitably adding several simple shortened pulses together some of the high energy harmonics are either further reduced or eliminated. This multilevel signal can be easily generated digitally and it enables simpler digital processing involving only additions and shifting. On the other hand required extra circuitry for multiple current levels should not eliminate main advantages of square wave excitation, such as reduced complexity and low consumption. Proposed solution improves the power consumption and reduces the complexity of the system as a whole compared to more generic approach. The current source output will be the shortened multilevel square wave signal. The output current value can be selected from range from 5 to 100 μA. The main advantage of this method is greater efficiency because for measuring cycle only one or two pairs of switchable current mirrors will be activated to drive the H-bridge.","PeriodicalId":271676,"journal":{"name":"2011 IEEE 9th International New Circuits and systems conference","volume":"104 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-06-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134046344","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A low power VLSI implementation of the Izhikevich neuron model Izhikevich神经元模型的低功耗VLSI实现
2011 IEEE 9th International New Circuits and systems conference Pub Date : 2011-06-26 DOI: 10.1109/NEWCAS.2011.5981282
A. S. Demirkol, S. Ozoguz
{"title":"A low power VLSI implementation of the Izhikevich neuron model","authors":"A. S. Demirkol, S. Ozoguz","doi":"10.1109/NEWCAS.2011.5981282","DOIUrl":"https://doi.org/10.1109/NEWCAS.2011.5981282","url":null,"abstract":"We present a low-power VLSI implementation of the Izhikevich neuron model utilizing two first-order log-domain filters as the main building block. One of the filters includes an active diode connection in order to lower current levels to obtain a low-power, large time constant design. Thus, the neuron circuit operates in sub-threshold regime with biological time scale. The possible applications of the presented implementation are simulating large scale VLSI neural networks and building hybrid interface systems. The simulation results demonstrate the success of replicating the firing patterns of real neurons.","PeriodicalId":271676,"journal":{"name":"2011 IEEE 9th International New Circuits and systems conference","volume":"275 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-06-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115883642","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 20
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