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2011 IEEE 9th International New Circuits and systems conference最新文献

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Linearity improvement thanks to the association of Active Constellation Extension and digital predistortion for OFDM 基于主动星座扩展和数字预失真的OFDM线性度改善
2011 IEEE 9th International New Circuits and systems conference Pub Date : 2011-06-26 DOI: 10.1109/NEWCAS.2011.5981313
M. Brandon, M. Ariaudo, S. Traverso, J. Bouvier, I. Fijalkow, J. Gautier
{"title":"Linearity improvement thanks to the association of Active Constellation Extension and digital predistortion for OFDM","authors":"M. Brandon, M. Ariaudo, S. Traverso, J. Bouvier, I. Fijalkow, J. Gautier","doi":"10.1109/NEWCAS.2011.5981313","DOIUrl":"https://doi.org/10.1109/NEWCAS.2011.5981313","url":null,"abstract":"Nonlinearity problems for power amplifiers are well known and many linearization techniques have been proposed in the literature, especially digital baseband predistortion. Orthogonal Frequency Division Multiplexing (OFDM) has a very high Peak-to-Average Power Ratio (PAPR), making it very sensitive to non linearities. We have chosen the Active Constellation Extension (ACE) to reduce the crest factor, which is not sufficient. In this paper, we show that the association of ACE with digital predistortion helps to improve the Adjacent Channel Power Ratio (ACPR) and so permits a good linearity improvement. The association is first validated in simulation. In measurements, for 42.5dBm RMS output power, which represents the nominal power, the ACPR is increased from 32dBc to 49dBc. For a given ACPR of 35dBc, the RMS output power is increased from 40.7dBm to 42.7dBm.","PeriodicalId":271676,"journal":{"name":"2011 IEEE 9th International New Circuits and systems conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-06-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123090109","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
Current-mirror based PID controller 基于电流镜的PID控制器
2011 IEEE 9th International New Circuits and systems conference Pub Date : 2011-06-26 DOI: 10.1109/NEWCAS.2011.5981312
V. Michal, C. Premont, G. Pillonnet, N. Abouchi
{"title":"Current-mirror based PID controller","authors":"V. Michal, C. Premont, G. Pillonnet, N. Abouchi","doi":"10.1109/NEWCAS.2011.5981312","DOIUrl":"https://doi.org/10.1109/NEWCAS.2011.5981312","url":null,"abstract":"In this paper, the architecture of the Proportional-Integration-Derivative (PID) controller, based on the current-difference amplifier, is presented. This architecture allows to integrate the controller, employing only four active MOS transistors. It also allows obtaining interesting features, such as the low power consumption, and high bandwidth, in spite of the low DC accuracy (offset). In this paper, basic design equations for the DC operation point setting, transfer function, and the MOS transistor sizing are provided. The performances are demonstrated by a simulation of the circuit designed in 40nm CMOS, employed to stabilize the feedback-loop of the switched DC/DC buck converter.","PeriodicalId":271676,"journal":{"name":"2011 IEEE 9th International New Circuits and systems conference","volume":"76 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-06-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129460583","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A low-noise parasitic-insensitive switched-capacitor CMOS interface circuit for MEMS capacitive sensors 一种用于MEMS电容式传感器的低噪声寄生不敏感开关电容CMOS接口电路
2011 IEEE 9th International New Circuits and systems conference Pub Date : 2011-06-26 DOI: 10.1109/NEWCAS.2011.5981272
Jack Shiah, H. Rashtian, S. Mirabbasi
{"title":"A low-noise parasitic-insensitive switched-capacitor CMOS interface circuit for MEMS capacitive sensors","authors":"Jack Shiah, H. Rashtian, S. Mirabbasi","doi":"10.1109/NEWCAS.2011.5981272","DOIUrl":"https://doi.org/10.1109/NEWCAS.2011.5981272","url":null,"abstract":"This paper describes a differential low-noise high-resolution parasitic-insensitive switched-capacitor readout circuit that is intended for capacitive sensors, in particular, for MEMS inertial sensory systems. The operation of the proposed readout front-end circuit is explained. Amplitude modulation/demodulation and correlated double sampling techniques are used in the interface circuit to minimize the undesirable effects of the amplifier offset and flicker (1/f) noise. The application of the aforementioned techniques also further improve the sensitivity of the readout circuit. The interface system is designed and laid out in a 0.8 μm CMOS process. Post-layout simulation results demonstrate that the circuit is capable of resolving input sense capacitance variations as low as 0.5 aF with a sensitivity of 9.98 mV/aF. The circuit consumes 8.38 mW from a single 5 V supply.","PeriodicalId":271676,"journal":{"name":"2011 IEEE 9th International New Circuits and systems conference","volume":"154 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-06-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133237236","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 13
A variable bandwidth & IF, continuous time ΔΣ modulator for low power low-IF receivers 用于低功率低中频接收机的可变带宽&中频，连续时间ΔΣ调制器
2011 IEEE 9th International New Circuits and systems conference Pub Date : 2011-06-26 DOI: 10.1109/NEWCAS.2011.5981245
A. Atac, R. Wunderlich, S. Heinen
{"title":"A variable bandwidth & IF, continuous time ΔΣ modulator for low power low-IF receivers","authors":"A. Atac, R. Wunderlich, S. Heinen","doi":"10.1109/NEWCAS.2011.5981245","DOIUrl":"https://doi.org/10.1109/NEWCAS.2011.5981245","url":null,"abstract":"This paper presents a novel continuous time ΔΣ modulator for multi-mode operation. The design is targeted for low power, low IF multi-mode receivers and could operate on any bandwidth ranging from 0.5MHz to 1.5MHz while using the same architecture. A 3rd order, quadrature bandpass (QBP) modulator is preferred that operates on a single side of the frequency spectrum and hence improves the noise shaping characteristic. Weighted capacitive feedforward (WCFF) method is developed and analyzed to achieve the required bandwidths and IF for multi-mode operation. The achieved SNR values are 68.7/60.6/50.4dB for 0.5/1/1.5MHz bandwidths respectively, while consuming a total average current of 1.8mA from a 1.2V supply. The design is simulated with UMC 0.13μm technology.","PeriodicalId":271676,"journal":{"name":"2011 IEEE 9th International New Circuits and systems conference","volume":"78 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-06-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133319530","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
Accurate extraction of inductively-affected delay using an optimized tapered partitioning scheme for global interconnects 采用优化的全局互连锥形分配方案精确提取感应影响延迟
2011 IEEE 9th International New Circuits and systems conference Pub Date : 2011-06-26 DOI: 10.1109/NEWCAS.2011.5981274
Zohreh Farjad, N. Masoumi
{"title":"Accurate extraction of inductively-affected delay using an optimized tapered partitioning scheme for global interconnects","authors":"Zohreh Farjad, N. Masoumi","doi":"10.1109/NEWCAS.2011.5981274","DOIUrl":"https://doi.org/10.1109/NEWCAS.2011.5981274","url":null,"abstract":"The delay caused by global interconnects plays a critical role in the performance of VLSI circuits, particularly for transmission effects in nano scales. This paper presents an analytical formulation for the delay of tapered partitioning scheme of buffer insertion in long global interconnects. The inductive effects have been taken into account in RLC delay expressions. Because of complexity of the expressions and various design parameters simulated annealing has been used to extract accurate optimum values for the parameters. Using this method, we have achieved 60% improvement in the delay reduction.","PeriodicalId":271676,"journal":{"name":"2011 IEEE 9th International New Circuits and systems conference","volume":"65 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-06-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133418883","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A 59GHz-to-67GHz 65nm-CMOS high efficiency Power Amplifier 59ghz - 67ghz 65nm cmos高效率功率放大器
2011 IEEE 9th International New Circuits and systems conference Pub Date : 2011-06-26 DOI: 10.1109/NEWCAS.2011.5981296
S. Aloui, E. Kerhervé, R. Plana, D. Belot
{"title":"A 59GHz-to-67GHz 65nm-CMOS high efficiency Power Amplifier","authors":"S. Aloui, E. Kerhervé, R. Plana, D. Belot","doi":"10.1109/NEWCAS.2011.5981296","DOIUrl":"https://doi.org/10.1109/NEWCAS.2011.5981296","url":null,"abstract":"A two-stage single-ended Power Amplifier (PA) is fabricated for the 60GHz Wireless Personal Area Network (WPAN) standard. It is based on the 65nm CMOS technology from STMicroelectronics. The PA is biased in class A and uses distributed elements to perform impedances matching. S-parameters and large signal simulations are validated by measurement results. Load pull measurements are performed to get the best operation of the PA. It achieves a saturated output power (Psat) of 12dB and offers Power Added Efficiency (PAE) of 15%. The die area is 0.29mm2 with pads.","PeriodicalId":271676,"journal":{"name":"2011 IEEE 9th International New Circuits and systems conference","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-06-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134034885","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
Two new balanced-input current-mode differential receivers for high-speed links 两个新的平衡输入电流模式差分接收器用于高速链路
2011 IEEE 9th International New Circuits and systems conference Pub Date : 2011-06-26 DOI: 10.1109/NEWCAS.2011.5981237
F. Broydé, E. Clavelier
{"title":"Two new balanced-input current-mode differential receivers for high-speed links","authors":"F. Broydé, E. Clavelier","doi":"10.1109/NEWCAS.2011.5981237","DOIUrl":"https://doi.org/10.1109/NEWCAS.2011.5981237","url":null,"abstract":"Two new balanced-input current-mode differential receivers for high-speed links have a low common-mode input admittance and a fairly linear differential-mode (DM) input characteristic, in addition to the linear transfer characteristic inherent to current-mode circuits. The DM input impedance may be such that no resistor is needed to reduce reflection.","PeriodicalId":271676,"journal":{"name":"2011 IEEE 9th International New Circuits and systems conference","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-06-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132127903","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A wavelet based baseline drift correction method for fetal magnetocardiograms 基于小波的胎儿心磁图基线漂移校正方法
2011 IEEE 9th International New Circuits and systems conference Pub Date : 2011-06-26 DOI: 10.1109/NEWCAS.2011.5981231
Beatrice Arvinti-Costache, M. Costache, C. Nafornita, A. Isar, R. Stolz, H. Toepfer
{"title":"A wavelet based baseline drift correction method for fetal magnetocardiograms","authors":"Beatrice Arvinti-Costache, M. Costache, C. Nafornita, A. Isar, R. Stolz, H. Toepfer","doi":"10.1109/NEWCAS.2011.5981231","DOIUrl":"https://doi.org/10.1109/NEWCAS.2011.5981231","url":null,"abstract":"The paper aims at the development of a method for the removal of baseline drift of fetal magnetocardiograms. The described method is based on wavelet analysis and uses the Stationary Wavelet Transform (SWT). The performance of the method is ensured through the appropriate preselection of two parameters: the mother wavelet used for the computation of the SWT and the number of decomposition levels, selected in accordance to the sampling frequency of the magnetocardiogram (MCG). The method is robust and can be used in an automatic processing system.","PeriodicalId":271676,"journal":{"name":"2011 IEEE 9th International New Circuits and systems conference","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-06-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122367179","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Novel high speed differential CMOS flip-flop for ultra low-voltage appications 用于超低电压应用的新型高速差分CMOS触发器
2011 IEEE 9th International New Circuits and systems conference Pub Date : 2011-06-26 DOI: 10.1109/NEWCAS.2011.5981300
Y. Berg
{"title":"Novel high speed differential CMOS flip-flop for ultra low-voltage appications","authors":"Y. Berg","doi":"10.1109/NEWCAS.2011.5981300","DOIUrl":"https://doi.org/10.1109/NEWCAS.2011.5981300","url":null,"abstract":"In this paper we present a novel ultra-low-voltage (ULV) CMOS flip-flop. The ULV flip-flop offers increased speed compared to other FF's for low supply voltages. The pulse generator (PG) circuit in a conventional sense amplifier SAFF is replaced by a high-speed tristate edge generator (EG) with a rise- and fall-time less than 1/10 of an inverter operating with the same supply voltage. In essence the delay of the ultra-low-voltage FF (UFF) presented in this paper is located in the latch stage. In terms of maximum operating frequency for ULV operation the UFF may be used at frequencies 10 times compared to more conventional FF's. The power-delay-product (PDP) of the UFF is significantly reduced accordingly. The simulated data presented is obtained using the Spectre simulator provided by Cadence and valid for a 90nm TMC CMOS process with inherent threshold voltages of 250mV. The transistors used for the low voltage FF are minimum sized.","PeriodicalId":271676,"journal":{"name":"2011 IEEE 9th International New Circuits and systems conference","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-06-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127083045","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
A phase error calibration DLL with edge combiner for wide-range operation 带边缘组合器的相位误差校准DLL，适用于大范围操作
2011 IEEE 9th International New Circuits and systems conference Pub Date : 2011-06-26 DOI: 10.1109/NEWCAS.2011.5981204
Po-Chun Huang, Chi-Jih Shih, Yu-Chang Tsai, Kuo-Hsing Cheng
{"title":"A phase error calibration DLL with edge combiner for wide-range operation","authors":"Po-Chun Huang, Chi-Jih Shih, Yu-Chang Tsai, Kuo-Hsing Cheng","doi":"10.1109/NEWCAS.2011.5981204","DOIUrl":"https://doi.org/10.1109/NEWCAS.2011.5981204","url":null,"abstract":"In this paper, a technique to reduce the output jitter and the wide-range operation is presented. A wide-range voltage controlled delay line (WRVCDL) uses multi-band to operate on wide-range. The proposed DLL operates from 25MHz to 250MHz. An edge combiner (EC) is used to increase the output frequency range. It synthesizes frequencies from 250MHz to 2.5GHz. The output of EC will be a 50% cycle in all different frequencies. The presented clock generator uses a dynamical phase detector (DPD) to effectively reduce the DLL output jitter from 7.81ps to 5.4ps at 250MHz. In simulation results which show the output jitter is from 16.2p to 11.7p at 2.5GHz by using the calibration. The static phase error of the proposed DLL reduced from 7.35ps to 2.1ps at 250MHz. The proposed DLL has been fabricated in 0.18μm 1P6M CMOS process. The total power consumption is 6.14mW in 2.5GHz with buffer and the core area is 0.033mm2.","PeriodicalId":271676,"journal":{"name":"2011 IEEE 9th International New Circuits and systems conference","volume":"2006 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-06-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125836290","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
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