Novel high speed differential CMOS flip-flop for ultra low-voltage appications

Abstract

In this paper we present a novel ultra-low-voltage (ULV) CMOS flip-flop. The ULV flip-flop offers increased speed compared to other FF's for low supply voltages. The pulse generator (PG) circuit in a conventional sense amplifier SAFF is replaced by a high-speed tristate edge generator (EG) with a rise- and fall-time less than 1/10 of an inverter operating with the same supply voltage. In essence the delay of the ultra-low-voltage FF (UFF) presented in this paper is located in the latch stage. In terms of maximum operating frequency for ULV operation the UFF may be used at frequencies 10 times compared to more conventional FF's. The power-delay-product (PDP) of the UFF is significantly reduced accordingly. The simulated data presented is obtained using the Spectre simulator provided by Cadence and valid for a 90nm TMC CMOS process with inherent threshold voltages of 250mV. The transistors used for the low voltage FF are minimum sized.