Power supply noise and ground bounce aware pattern generation for delay testing

Abstract

Power supply noise and ground bounce can significantly impact the circuit's performance. Existing delay testing techniques do not capture the impact of combined and uncorrelated power supply noise and ground bounce for critical path delay analysis. They capture the worst case power supply noise in order to obtain the worst case path delay. We show that such assumption is not necessarily sufficient and combined effects of both power and ground noise should be considered for path delay analysis. First, we propose accurate close-form mathematical models for capturing the path delay variations in the presence of power supply noise and ground bounce. We utilize these models as the fitness function for pattern generation technique which is a simulated annealing based iterative process. In our experiments, we show that path delay variation can be significant if test patterns are not properly selected.