A low power VLSI implementation of the Izhikevich neuron model

Abstract

We present a low-power VLSI implementation of the Izhikevich neuron model utilizing two first-order log-domain filters as the main building block. One of the filters includes an active diode connection in order to lower current levels to obtain a low-power, large time constant design. Thus, the neuron circuit operates in sub-threshold regime with biological time scale. The possible applications of the presented implementation are simulating large scale VLSI neural networks and building hybrid interface systems. The simulation results demonstrate the success of replicating the firing patterns of real neurons.