The design and assessment of a secure passive RFID sensor system

Abstract

This paper presents a low-overhead security enhancement for EPC Class-1 Generation-2 (Gen2) compatible RFID tags that provides data confidentiality for a series of common threats. The new security circuit, based on the PRESENT block cipher, is fully integrated into a passive RFID tag architecture. The circuit is evaluated in an FPGA-based emulation platform which allows for the validation of the circuit and the use of a protocol which seamlessly interacts with a standard off-the-shelf RFID reader. A complete system, including a temperature sensor attached to the emulated tag, was successfully tested in the lab using an existing Gen2 RFID reader. The hardware overhead of the security enhancement is roughly 1,900 logic gates.