发布求助
文献互助 智能选刊 最新文献

2020 International SoC Design Conference (ISOCC)最新文献

筛选
英文 中文
Design of Current-Mode 8T SRAM Compute-In-Memory Macro for Processing Neural Networks 用于处理神经网络的电流模式8T SRAM内存计算宏的设计
2020 International SoC Design Conference (ISOCC) Pub Date : 2020-10-21 DOI: 10.1109/ISOCC50952.2020.9332992
Taegeun Yoo, T. T. Kim, Bongjin Kim, Chengshuo Yu, Kevin Chai Tshun Chuan
{"title":"Design of Current-Mode 8T SRAM Compute-In-Memory Macro for Processing Neural Networks","authors":"Taegeun Yoo, T. T. Kim, Bongjin Kim, Chengshuo Yu, Kevin Chai Tshun Chuan","doi":"10.1109/ISOCC50952.2020.9332992","DOIUrl":"https://doi.org/10.1109/ISOCC50952.2020.9332992","url":null,"abstract":"A novel 8T SRAM bitcell is proposed for computing dot-products using current-mode accumulation. A write disturb issue has been eliminated by adding two extra transistors into a standard 6T SRAM bitcell. Besides, we embed a column ADC in each column-based neuron to address the ADC overhead issue of conventional analog compute-in-memory macros. The resolution of ADC is reconfigurable from 1 to 5bit. A test-chip is fabricated using 65nm, and the energy-efficiency of bitwise operation is 490-to-15.8TOPS/W at 1-5bit.","PeriodicalId":270577,"journal":{"name":"2020 International SoC Design Conference (ISOCC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2020-10-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131574122","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
An Efficient Sensory System for Intelligent Gas Monitoring Accurate classification and precise quantification of gases/ odors 气体/气味的准确分类和精确量化
2020 International SoC Design Conference (ISOCC) Pub Date : 2020-10-21 DOI: 10.1109/ISOCC50952.2020.9332957
A. Mishra, Shiho Kim, N. S. Rajput
{"title":"An Efficient Sensory System for Intelligent Gas Monitoring Accurate classification and precise quantification of gases/ odors","authors":"A. Mishra, Shiho Kim, N. S. Rajput","doi":"10.1109/ISOCC50952.2020.9332957","DOIUrl":"https://doi.org/10.1109/ISOCC50952.2020.9332957","url":null,"abstract":"Intelligent gas monitoring system is having its widespread applications. It essentially requires an accurate classification with precise quantification of gases/odors. Although, gas sensor arrays are capable of generating signatures however, mostly these signatures are complex and have subtle information. Therefore, in this paper, an efficient sensory system has been proposed for intelligent gas monitoring. Concept of analysis space transformation has been utilized for accurate classification of gases/ odors. Also, the drawback of data preprocessing in quantification has been illustrated by comparing the quantifier performance for the processed and raw responses. Further, the proposed sensory system has elevated the classification accuracy from 96% to 98.74% along with the quantification accuracy from 17.65% to 94%.","PeriodicalId":270577,"journal":{"name":"2020 International SoC Design Conference (ISOCC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2020-10-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131582773","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Digital-to-Analog Converter Architectures Based on Polygonal and Prime Numbers 基于多边形和素数的数模转换器结构
2020 International SoC Design Conference (ISOCC) Pub Date : 2020-10-21 DOI: 10.1109/ISOCC50952.2020.9333102
Yuanyang Du, Xueyan Bai, Manato Hirai, Shuhei Yamamoto, A. Kuwana, Haruo Kobayashi, K. Kubo
{"title":"Digital-to-Analog Converter Architectures Based on Polygonal and Prime Numbers","authors":"Yuanyang Du, Xueyan Bai, Manato Hirai, Shuhei Yamamoto, A. Kuwana, Haruo Kobayashi, K. Kubo","doi":"10.1109/ISOCC50952.2020.9333102","DOIUrl":"https://doi.org/10.1109/ISOCC50952.2020.9333102","url":null,"abstract":"This paper describes new configurations of digital-to-analog converters (DACs) based on number theory: (i) DACs consisting of N current sources, N-angle number weighted resistor networks, switch arrays and decoders (N= 3, 4, 5,…). (ii) A DAC composed of two current sources, a prime number weighted resistor network, switch array, a decoder; this is based on Goldbach's conjecture in the number theory. Their principles, configurations and operations are presented.","PeriodicalId":270577,"journal":{"name":"2020 International SoC Design Conference (ISOCC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2020-10-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128201300","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Design of a CMOS Current-mode Squaring Circuit for Training Analog Neural Networks 用于模拟神经网络训练的CMOS电流模平方电路设计
2020 International SoC Design Conference (ISOCC) Pub Date : 2020-10-21 DOI: 10.1109/ISOCC50952.2020.9333090
Soyoun Park, Jae-Hee Lee, Hang-Geun Jeong, D. Im
{"title":"Design of a CMOS Current-mode Squaring Circuit for Training Analog Neural Networks","authors":"Soyoun Park, Jae-Hee Lee, Hang-Geun Jeong, D. Im","doi":"10.1109/ISOCC50952.2020.9333090","DOIUrl":"https://doi.org/10.1109/ISOCC50952.2020.9333090","url":null,"abstract":"We propose a new current mode CMOS squaring circuit which directly yields the square term. The proposed squaring circuit was designed in a standard with 0.18 µm CMOS technology. The designed chip occupies a chip area of 408µm × 197µm and consumes a power of 3.6mW. The proposed squaring circuit can be used in current mode applications as in analog neurons.","PeriodicalId":270577,"journal":{"name":"2020 International SoC Design Conference (ISOCC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2020-10-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"113969431","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Design of a Low-Cost Approximate Adder with a Zero Truncation 零截断低成本近似加法器的设计
2020 International SoC Design Conference (ISOCC) Pub Date : 2020-10-21 DOI: 10.1109/ISOCC50952.2020.9332971
Jungwon Lee, Hyoju Seo, Yerin Kim, Yongtae Kim
{"title":"Design of a Low-Cost Approximate Adder with a Zero Truncation","authors":"Jungwon Lee, Hyoju Seo, Yerin Kim, Yongtae Kim","doi":"10.1109/ISOCC50952.2020.9332971","DOIUrl":"https://doi.org/10.1109/ISOCC50952.2020.9332971","url":null,"abstract":"We propose a cost-effective approximate adder using a zero truncation technique with acceptable accuracy. The proposed adder design reduces the area by up to 23% compared to the approximate adders considered in this paper when implemented with a 32-nm CMOS technology. Furthermore, our adder shows 16%, 10%, 10%, and 16% better performance in area, power, power-delay product, and area-delay product, respectively, than the lower-part OR adder while providing an acceptable accuracy performance. To see the impact of approximation errors caused by our adder on real applications, it is adopted in a digital image processing and demonstrates that our adder rarely affects the output image quality.","PeriodicalId":270577,"journal":{"name":"2020 International SoC Design Conference (ISOCC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2020-10-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121220368","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
A Low Noise MEMS Based CMOS Resonator Using Magnetoelectric Sensor 基于磁电传感器的低噪声MEMS CMOS谐振器
2020 International SoC Design Conference (ISOCC) Pub Date : 2020-10-21 DOI: 10.1109/ISOCC50952.2020.9332807
Mehdi Nasrollahpour, Alexei D. Matyushov, Mohsen Zaeimbashi, N. Sun
{"title":"A Low Noise MEMS Based CMOS Resonator Using Magnetoelectric Sensor","authors":"Mehdi Nasrollahpour, Alexei D. Matyushov, Mohsen Zaeimbashi, N. Sun","doi":"10.1109/ISOCC50952.2020.9332807","DOIUrl":"https://doi.org/10.1109/ISOCC50952.2020.9332807","url":null,"abstract":"This paper presents a miniaturized complementary-metal-oxide-semiconductor (CMOS) oscillator using microelectromechanical system (MEMS) resonating at 159 MHz frequency. The CMOS circuit is designed and simulated in 0.35,..,m XFAB technology. The fabricated magnetoelectric (ME) sensor offers quality factor of 653. The proposed oscillator provides a phase noise as low as -131.3 dBc/Hz at 10kHz and -137.9 dBc/Hz at 100 kHz offset frequencies while consuming 2.24 mW power.","PeriodicalId":270577,"journal":{"name":"2020 International SoC Design Conference (ISOCC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2020-10-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121256661","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Variable Length MAC for CAN Security Protocol 可变长度MAC为CAN安全协议
2020 International SoC Design Conference (ISOCC) Pub Date : 2020-10-21 DOI: 10.1109/ISOCC50952.2020.9333089
Yeonjin Kim, Jin-Gyun Chung
{"title":"Variable Length MAC for CAN Security Protocol","authors":"Yeonjin Kim, Jin-Gyun Chung","doi":"10.1109/ISOCC50952.2020.9333089","DOIUrl":"https://doi.org/10.1109/ISOCC50952.2020.9333089","url":null,"abstract":"Controller area network (CAN) was introduced by Bosch in 1986. CAN has been commonly used in vehicles due to its high reliability and low cost. Over the past decade, the possibilities for security attacks in vehicles have been increasing and have been reported in several papers. However, security issues have not been treated properly in CAN. In this paper, we propose a security protocol based on the data compression algorithm.","PeriodicalId":270577,"journal":{"name":"2020 International SoC Design Conference (ISOCC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2020-10-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129263073","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Low-cost Hardware Architecture for Integral Image Generation using Word Length Reduction 基于字长缩减的集成图像生成的低成本硬件架构
2020 International SoC Design Conference (ISOCC) Pub Date : 2020-10-21 DOI: 10.1109/ISOCC50952.2020.9332974
Junghwan Kim, Jongkil Hyun, Byungin Moon
{"title":"Low-cost Hardware Architecture for Integral Image Generation using Word Length Reduction","authors":"Junghwan Kim, Jongkil Hyun, Byungin Moon","doi":"10.1109/ISOCC50952.2020.9332974","DOIUrl":"https://doi.org/10.1109/ISOCC50952.2020.9332974","url":null,"abstract":"An integral image is widely used in face detection to calculate feature values at high speed. However, implementing integral images in hardware requires considerable logic and memory resources. This paper proposes a hardware architecture for integral image generation with reduced resource usage by applying the word length reduction method. When implemented in an FPGA, the proposed architecture uses about 83% fewer Slice LUTs than the conventional integral image method. Therefore, the proposed architecture is suitable for low-cost realtime face detection systems.","PeriodicalId":270577,"journal":{"name":"2020 International SoC Design Conference (ISOCC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2020-10-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115869585","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Maintaining Images by Cellular Neural Networks with Switching Two Templates 切换两个模板的细胞神经网络图像维护
2020 International SoC Design Conference (ISOCC) Pub Date : 2020-10-21 DOI: 10.1109/ISOCC50952.2020.9332939
K. Kitamura, Y. Uwate, Y. Nishio
{"title":"Maintaining Images by Cellular Neural Networks with Switching Two Templates","authors":"K. Kitamura, Y. Uwate, Y. Nishio","doi":"10.1109/ISOCC50952.2020.9332939","DOIUrl":"https://doi.org/10.1109/ISOCC50952.2020.9332939","url":null,"abstract":"The Cellular Neural Networks (CNN) was developed by Chua and Yang in 1998. The performance of the CNN depends on the parameters which are called the template. The CNN is applied to various image processing by changing the template. The output image processed by CNN is a binary image. Therefore, the unnecessary objects are removed in the process. In this research, we propose a method of switching two templates to stop the image processing in a certain state and output in the grayscale state.","PeriodicalId":270577,"journal":{"name":"2020 International SoC Design Conference (ISOCC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2020-10-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117056051","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Nonlinear Time Series Analysis of Spike Data of Izhikevich Neuron Model Izhikevich神经元模型峰值数据的非线性时间序列分析
2020 International SoC Design Conference (ISOCC) Pub Date : 2020-10-21 DOI: 10.1109/ISOCC50952.2020.9333002
Y. Uwate, Y. Nishio, M. Obien, U. Frey
{"title":"Nonlinear Time Series Analysis of Spike Data of Izhikevich Neuron Model","authors":"Y. Uwate, Y. Nishio, M. Obien, U. Frey","doi":"10.1109/ISOCC50952.2020.9333002","DOIUrl":"https://doi.org/10.1109/ISOCC50952.2020.9333002","url":null,"abstract":"It is well known that burst patterns of neuronal networks may play an important role in information processing in the brain. We consider that it is advantageous to construct a model using mathematical neuronal models producing burst patterns, because it is such models are easier to study and more accessible as compared to real biological neuronal data. In this study, we use the Izhikevich neuron model to produce burst patterns and apply a recurrence plot density entropy to the Izhikevich neuron data.","PeriodicalId":270577,"journal":{"name":"2020 International SoC Design Conference (ISOCC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2020-10-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115263155","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
首页 上一页 下一页 尾页
0
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
提示
您的信息不完整，为了账户安全，请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
现在去查看 取消
×
提示
确定
请完成安全验证×
相关产品
×
本文献相关产品
联系我们：info@booksci.cn Book学术提供免费学术资源搜索服务，方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。 Copyright © 2023 布克学术 All rights reserved.
京ICP备2023020795号-1
ghs 京公网安备 11010802042870号
Book学术文献互助
Book学术文献互助群
群 号：481959085
Book学术官方微信