{"title":"Robust performance analysis of a controlled synchronous machine","authors":"O. Akhrif, L. Saydy","doi":"10.1109/CCECE.1996.548222","DOIUrl":"https://doi.org/10.1109/CCECE.1996.548222","url":null,"abstract":"In this work we investigate the robust performance of a controller which was originally proposed by M. Araki et al. (see Eighth IFAC World Congress, Kyoto, Japan, p.3123-35, 1981) to control a synchronous machine connected to an infinite bus through a transmission line. The objectives of the design by Araki et. al. were to ensure (1) satisfactory voltage regulation in the pre-fault state and (2) satisfactory transient response in the post-fault state. The pre-fault and post-fault states are characterized by two extreme values of the line reactance X/sub e/, namely X/sub e1/=0.5 and X/sub e2/=0.8. However, as pointed out by Araki et. al., the controller is required to exhibit a satisfactory performance for a variety of operating conditions. In this article we analyze the robustness of the proposed controller for an uncertain value of the line reactance X/sub e/.","PeriodicalId":269440,"journal":{"name":"Proceedings of 1996 Canadian Conference on Electrical and Computer Engineering","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-05-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115155534","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Modeling of medium voltage smart motor controllers (MV SMC) in PSPICE","authors":"D. Raonic","doi":"10.1109/CCECE.1996.548233","DOIUrl":"https://doi.org/10.1109/CCECE.1996.548233","url":null,"abstract":"Computer-aided analysis and synthesis of power electronics circuits provides a powerful and economic insight into MV smart motor controllers. Although the PSPICE software contains a library of specific semiconductor devices including SCRs, the programmability of a thyristor model is required. A thyristor model featuring programmable on-resistance and reverse recovery time was proposed by Losic (1988) and is used in this work. In this case gate triggering and controllable reverse recovery time are of great importance.","PeriodicalId":269440,"journal":{"name":"Proceedings of 1996 Canadian Conference on Electrical and Computer Engineering","volume":"60 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-05-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123454184","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"SCR harmonic correction topologies for VSI drives","authors":"J. Salmon, E. Bocancea, R. Bhargava, E. Nowicki","doi":"10.1109/CCECE.1996.548321","DOIUrl":"https://doi.org/10.1109/CCECE.1996.548321","url":null,"abstract":"The circuit topologies described in this paper contribute to the technology of converting three-phase AC power to DC, with the prime application being the input stage to commercial variable speed VSI drives. The power converter topologies examined are essentially SCR harmonic correction units (HCUs) suitable as a retrofit or as a drive option. The elementary HCU uses a three-phase switch network to sequentially access each line voltage. Current pulses are drawn from the selected line voltage and low distortion line currents are drawn as a result. Each HCU topology has a hard switched and a resonant soft-switch version. Since the HCUs are separate to the main drive structure, drive operation can be maintained even if the unit fails. Alternatively, when low current total harmonic distortion is not required, the drive can be installed without the HCU to lower the drive cost. The performance of the power converters described in this paper are illustrated with reference to simulated and experimental data.","PeriodicalId":269440,"journal":{"name":"Proceedings of 1996 Canadian Conference on Electrical and Computer Engineering","volume":"71 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-05-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124515570","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Performance evaluation of bursty traffic using neural networks","authors":"H. Mehrvar, T. Le-Ngoc, J. Huang","doi":"10.1109/CCECE.1996.548312","DOIUrl":"https://doi.org/10.1109/CCECE.1996.548312","url":null,"abstract":"We investigate the application of neural networks to evaluate the performance, packet loss probability, of a bursty traffic stream. We show, that in a bursty multimedia environment, performance is a function of burstiness, Hurst parameter, traffic intensity and buffer size. In a closed loop traffic control system each source uses this reported measure to regulate their traffic to the destination queue. A multilayer neural network is used to capture the functional relationship between the loss probability and the traffic descriptor (Hurst parameter and traffic intensity) for a fixed value of buffer size. The neural network approach makes practical real-time performance measurement and hence the control of traffic in an adaptive environment.","PeriodicalId":269440,"journal":{"name":"Proceedings of 1996 Canadian Conference on Electrical and Computer Engineering","volume":"257 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-05-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122940475","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A radio transmitter fingerprinting system ODO-1","authors":"J. Toonstra, Witold Kinsner","doi":"10.1109/CCECE.1996.548038","DOIUrl":"https://doi.org/10.1109/CCECE.1996.548038","url":null,"abstract":"This paper presents a new method for the capture, analysis, and classification of radio transmitter transients. This method involves the use of a capturing subsystem consisting of an Icom IC-R7000 communications receiver and a Sound Blaster 16 sound card running on a PC. The radio transients are sampled at 44,100 samples per second and have 16 bits accuracy. Once the transmitter transient has been captured, a genetic algorithm selects the critical features from the wavelet coefficients for classification. The selected wavelet coefficients are considered to be fingerprints, and are presented to a back propagation neural network for transmitter classification. The capturing and analysis system, ODO-1, is able to classify both transients of the same model type as well as individual transmitters with 100% accuracy on a small data base of transmitter fingerprints.","PeriodicalId":269440,"journal":{"name":"Proceedings of 1996 Canadian Conference on Electrical and Computer Engineering","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-05-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121804391","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Self-bias for Class B bipolar transistors","authors":"J. McRory, R. Johnston","doi":"10.1109/CCECE.1996.548287","DOIUrl":"https://doi.org/10.1109/CCECE.1996.548287","url":null,"abstract":"It is well recognized that the BJT Class B amplifier's conduction angle and gain are dependent on the amplifier's input power level. This dependence is most apparent at lower input signal levels where the transistor is barely turned on. This paper presents an alternative bias network to be used with Class B BJT amplifiers which will compensate for low input power level, resulting in a more constant conduction angle, power gain and input impedance. The results of a simulation experiment which compares the performance of two Class B DC bias circuits for bipolar power transistors as used in a single ended resistive Class B power amplifier are examined.","PeriodicalId":269440,"journal":{"name":"Proceedings of 1996 Canadian Conference on Electrical and Computer Engineering","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-05-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122652122","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Objective image quality measures for evaluating advanced MRI reconstruction methods","authors":"T. Mathews, M.R. Smith","doi":"10.1109/CCECE.1996.548111","DOIUrl":"https://doi.org/10.1109/CCECE.1996.548111","url":null,"abstract":"We propose some new objective image quality measures for use with magnetic resonance images. These measures are based on the visual differences predictor (VDP) due to Daly (1992,1993). The VDP is a computer program that implements a complex model of the human visual system, and generates a map indicating the probability of the visual system perceiving a difference between two images on a pixel by pixel basis. A brief overview of the VDP algorithm is given, and the image quality measures we have developed based on the VDP are then described. The preliminary validation methods used to evaluate these image quality measures are then given. The results of these preliminary investigations indicate that these measures are promising as useful indicators of perceived image quality.","PeriodicalId":269440,"journal":{"name":"Proceedings of 1996 Canadian Conference on Electrical and Computer Engineering","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-05-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123843992","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Novel alpha-transform distance relaying scheme","authors":"A. Sharaf, R. El-Sharkawy, H. Talaat, M. Badr","doi":"10.1109/CCECE.1996.548262","DOIUrl":"https://doi.org/10.1109/CCECE.1996.548262","url":null,"abstract":"This paper presents a simple novel distance relaying scheme based on the 3-D alpha (/spl alpha/)-hyperplane of (V/sub /spl alpha//- I/sub /spl alpha//- P/sub /spl alpha//) representing the relay location measurement at the bus. The nonlinearly transformed voltage, current and apparent power carries information about the fault location and fault condition as bolted or high impedance faults (HIF). The paper describes the tripping mechanism and fault detection conditions in the /spl alpha/-hyperplane for transmission line distance relaying. The scheme is both simple and novel and takes into consideration the quasi dynamic nature of the faults, fault impedance nonlinearity and transmission line capacitance backfeed and resonant oscillations causing amplitude modulation of transmission line segment phase currents. The relay can be easily implemented using analog/digital or hybrid hardware. The relay is based on a transient model and includes all asymmetry and nonlinearity associated with different fault types, fault location, preloading and voltage power angles. The detection is based on transformed /spl alpha/-variables (V, I, P).","PeriodicalId":269440,"journal":{"name":"Proceedings of 1996 Canadian Conference on Electrical and Computer Engineering","volume":"244 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-05-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125313899","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Current-mode A/D converter architectures for integrated sensor systems","authors":"B. Lye, M. Syrzycki","doi":"10.1109/CCECE.1996.548070","DOIUrl":"https://doi.org/10.1109/CCECE.1996.548070","url":null,"abstract":"This paper presents several Current-Mode A/D converters that have been designed for use in Integrated Sensor Systems. Four designs, two binary-coded pipelined and two Sigma-Delta based, are presented and are compared in terms of resolution, circuit complexity and power dissipation, and conclusions are made about their suitability for use in Integrated Sensor Systems.","PeriodicalId":269440,"journal":{"name":"Proceedings of 1996 Canadian Conference on Electrical and Computer Engineering","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-05-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130272584","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Variance reduction techniques for use with sequential Monte Carlo simulation in bulk power system reliability evaluation","authors":"R. Billinton, A. Jonnavithula","doi":"10.1109/CCECE.1996.548125","DOIUrl":"https://doi.org/10.1109/CCECE.1996.548125","url":null,"abstract":"Estimation of composite system adequacy indices using sequential Monte Carlo simulation approach with time varying loads at each load bus is computationally quite expensive. Variance reduction techniques (VRT) can be used together with the sequential simulation process to enhance the efficiency of the simulation. This paper discusses two commonly used VRTs-control variates (CV) and antithetic variates (AV) with reference to the sequential simulation method used for adequacy analysis. Case studies are conducted on a representative power system network.","PeriodicalId":269440,"journal":{"name":"Proceedings of 1996 Canadian Conference on Electrical and Computer Engineering","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-05-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124798685","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}