Yong-Il Kwon, Sangkyu Park, T. Park, Hai-Young Lee
{"title":"A fully integrated 2.4-GHz CMOS diversity receiver with a novel antenna selection","authors":"Yong-Il Kwon, Sangkyu Park, T. Park, Hai-Young Lee","doi":"10.1109/RFIC.2010.5477304","DOIUrl":"https://doi.org/10.1109/RFIC.2010.5477304","url":null,"abstract":"A new low-complexity antenna diversity architecture, using a 2.4-GHz single low-IF receiver chain with a novel antenna selection scheme, is exploited by using 0.18-µm CMOS technology. The receiver has been developed for the IEEE standard 802.15.4 radio system and two RF input channels are selected through an efficient analog-type antenna selection scheme for achieving the diversity. Compared to conventional receivers without diversity, 10∼15 dB improvement of the received signal strength (RSS) has been measured for non-line-of-sight (NLOS) channels. By incorporating a wake-up function for the baseband blocks, the receiver operates at a very low power of 8.5 mW, with a 1.8 V power supply in the standby mode for receiving. The antenna selection error is negligible (≪1 %) and the antenna selection time is very fast (≪20 µs).","PeriodicalId":269027,"journal":{"name":"2010 IEEE Radio Frequency Integrated Circuits Symposium","volume":"136 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132706276","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"200GHz fT SiGe HBT load pull characterization at mm-wave frequencies","authors":"L. Boglione, R. T. Webster","doi":"10.1109/RFIC.2010.5477275","DOIUrl":"https://doi.org/10.1109/RFIC.2010.5477275","url":null,"abstract":"The load pull measurement of a commercially available SiGe HBT device has been performed at Q band over frequency and bias. Measured mm-wave results for the SiGe process under test have never been made available to the general public before and no comparable information on similar SiGe devices is available in the public domain. The goal of this paper is to begin to fill this gap: load pull results along with a discussion of the characterization setup and procedure are presented.","PeriodicalId":269027,"journal":{"name":"2010 IEEE Radio Frequency Integrated Circuits Symposium","volume":"601 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116306203","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Jian Liu, Lin Lin, Xin Wang, H Zhao, He Tang, Q. Fang, Albert Z. H. Wang, Hongyi Chen, Haolu Xie, S. Fan, B. Zhao, Gary Zhang
{"title":"Vast-fast low-triggering LTdSCR ESD protection structure for RF ICs in CMOS","authors":"Jian Liu, Lin Lin, Xin Wang, H Zhao, He Tang, Q. Fang, Albert Z. H. Wang, Hongyi Chen, Haolu Xie, S. Fan, B. Zhao, Gary Zhang","doi":"10.1109/RFIC.2010.5477278","DOIUrl":"https://doi.org/10.1109/RFIC.2010.5477278","url":null,"abstract":"This paper reports design of a novel low-parasitic ultra-low-triggering voltage dual-directional LTdSCR ESD protection structure in foundry CMOS. It features programmable low triggering voltage of 4.7∼6V, low discharging resistance of ∼0.77Ω, low leakage of ∼0.1nA, extremely low parasitic capacitance of ∼10fF and ultra fast response of ∼100ps. it achieves ESD protection of ≫7.8kV HBM and ∼500V CDM for a 90µm device. Measurement matches simulation very well. This low-parasitic low-triggering ESD protection structure is suitable for high data rate and low-voltage RF ICs in CMOS.","PeriodicalId":269027,"journal":{"name":"2010 IEEE Radio Frequency Integrated Circuits Symposium","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130191191","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Multi-mode WCDMA power amplifier module with improved low-power efficiency using stage-bypass","authors":"G. Hau, Mahendra Singh","doi":"10.1109/RFIC.2010.5477320","DOIUrl":"https://doi.org/10.1109/RFIC.2010.5477320","url":null,"abstract":"This paper presents a multi-mode power amplifier (PA) with very low DC quiescent current and current consumption under large power backoff operation. The PA is optimized to operate in three power modes. A dual-path PA is designed for high- and medium-power-mode operations, while a stage-bypass is applied to the final stage of the medium-power PA for low-power-mode operation. Load impedance for each power mode is individually optimized for best efficiency and linearity, achieving significant current saving compared to two-power-mode PAs. A 1.95GHz WCDMA PA module (PAM) has been developed using GaAs BiFET technology to validate the proposed circuit. The PAM demonstrates a very low quiescent current of 3.5mA under low-power-mode bias. The PAM exhibits 42% PAE and −40dBc ACLR1 at 28.5dBm Pout. At 17dBm and 8dBm backoff Pout, the PAM achieves 22% and 15% PAE, respectively, with −40dBc ACLR1. The current consumption at 8dBm Pout is reduced by 59% with the stage-bypass configuration.","PeriodicalId":269027,"journal":{"name":"2010 IEEE Radio Frequency Integrated Circuits Symposium","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130401198","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A 44-GHz 8-element phased-array SiGe HBT transmitter RFIC with an injection-locked quadrature frequency multiplier","authors":"Sunghwan Kim, P. Gudem, L. Larson","doi":"10.1109/RFIC.2010.5477253","DOIUrl":"https://doi.org/10.1109/RFIC.2010.5477253","url":null,"abstract":"An 8-element 44-GHz phased-array direct up-conversion transmitter, based on a localized injection-locked quadrature oscillator, is fabricated in a SiGe HBT process. The transmitter includes an improved injection-locked quadrature frequency doubler, an LO active phase shifter, I/Q mixers, and an RF PA driver. The transmitter has approximately 20-dB conversion gain per element, continuous 360° phase-shift and a baseband I/Q bandwidth of 2.2-GHz. The maximum saturated RF output power is 2-dBm at 45-GHz. Each element consumes 450mW. The chip size, including the pads, is 3×2.4 mm2.","PeriodicalId":269027,"journal":{"name":"2010 IEEE Radio Frequency Integrated Circuits Symposium","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129904358","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A 2-MHz bandwidth Δ-Σ fractional-N synthesizer based on a fractional frequency divider with digital spur suppression","authors":"Pin-en Su, S. Pamarti","doi":"10.1109/RFIC.2010.5477398","DOIUrl":"https://doi.org/10.1109/RFIC.2010.5477398","url":null,"abstract":"A 2-MHz delta-sigma fractional-N frequency synthesizer based on a staggered switching fractional frequency divider is presented in this paper. The phase generator based fractional frequency divider provides lower instantaneous phase error and hence lowers the delta-sigma quantization noise, so that the synthesizer loop bandwidth can be increased. To suppress fractional spurs due to phase generator phase errors, a digital spurious tone suppression technique is adopted. The frequency synthesizer is implemented in 0.18-µm CMOS process, and it operates at 2.1-GHz carrier frequency with 2-MHz bandwidth. Excluding the output buffer, the synthesizer consumes 33.9-mA and is capable of transmitting 4-Mb/s GFSK signal.","PeriodicalId":269027,"journal":{"name":"2010 IEEE Radio Frequency Integrated Circuits Symposium","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121057178","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Modeling of SOI FET for RF switch applications","authors":"Tzung-yin Lee, Sunyoung Lee","doi":"10.1109/RFIC.2010.5477300","DOIUrl":"https://doi.org/10.1109/RFIC.2010.5477300","url":null,"abstract":"This paper presents the modeling of an SOI FET for RF switch applications. Given that the HF small-signal predictability, i.e. the insertion loss and the isolation, is a common state of the art, the study focuses on the modeling of the non-linearity of the FET. The non-linearity of an SOI FET switch arises from not just the transistor, but also the SOI substrate through various mechanisms. First the non-linearity is caused by the voltage imbalance, a direct result of the substrate loss, in a switch made of many FETs stacked in series. The voltage imbalance is the main non-linearity contributor to a FET switch at high-power levels. Secondly the substrate itself is non-linear and sets the harmonic floor. Besides the substrate, the impact of other important SOI physics, such as the floating-body effect and the parasitic BJT effect, to the switch linearity will also be discussed. Finally a hybrid model that combines PSP as the FET core and a layout-dependent non-linear SOI substrate model is presented, and excellent non-linearity predictability was demonstrated on a real-life RF switch.","PeriodicalId":269027,"journal":{"name":"2010 IEEE Radio Frequency Integrated Circuits Symposium","volume":"64 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115327212","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Compact transformer power combiners for millimeter-wave wireless applications","authors":"Yi Zhao, J. Long, M. Spirito","doi":"10.1109/RFIC.2010.5477373","DOIUrl":"https://doi.org/10.1109/RFIC.2010.5477373","url":null,"abstract":"Two current-summing transformer combiners for 60GHz-band power amplification in millimeter-wave wireless applications are characterized. The parasitic-compensated balun and fully-differential combiners mitigate imbalances caused by interwinding capacitance, while self-shielded output windings inhibit substrate coupling. Excellent agreement is seen between measurement and electromagnetic simulation. Power loss for both prototypes at 60GHz is ≪1.0dB and chip area is ≪0.015mm2. Reflected impedance uniformity between ports at 60GHz for the balun and fully-differential combiners is better than 2.4% and 4.5%, respectively. A lumped-element model for large-signal circuit design with ≪5.0% error in power loss and reflected port impedance across the 55–65GHz band is also described.","PeriodicalId":269027,"journal":{"name":"2010 IEEE Radio Frequency Integrated Circuits Symposium","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131111709","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
M. El Hassan, E. Kerhervé, Y. Deval, J. David, D. Belot
{"title":"Tunability of Bulk Acoustic Wave filters using CMOS transistors: concept, design and implementation","authors":"M. El Hassan, E. Kerhervé, Y. Deval, J. David, D. Belot","doi":"10.1109/RFIC.2010.5477382","DOIUrl":"https://doi.org/10.1109/RFIC.2010.5477382","url":null,"abstract":"This paper presents the feasibility of a new method to tune the Bulk Acoustic Wave - Solidly Mounted Resonator (BAW-SMR) filters by adding capacitors to the shunt resonators and by controlling these capacitors using CMOS transistors that act as switches. The tunable BAWSMR filter is realized in a ladder topology. It is used for the 802.11b/g standard (2.40 – 2.48 GHz). Mainly, the filter fulfills the requirements for the WLAN 802.11 b/g standard, presenting a measured −3.3 dB of insertion loss, −12.7 dB of return loss and selectivity higher than 33 dB @ ± 30 MHz of the bandwidth. Moreover, a measured shift of 0.5% of the centre frequency (2.44 GHz) towards higher frequencies is obtained. This tunable BAW-SMR filter has reduced dimensions (1035*1075 µm2).","PeriodicalId":269027,"journal":{"name":"2010 IEEE Radio Frequency Integrated Circuits Symposium","volume":"164 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126220102","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A 2.2 mW regenerative FM-UWB receiver in 65 nm CMOS","authors":"N. Saputra, J. Long, J. Pekarik","doi":"10.1109/RFIC.2010.5477268","DOIUrl":"https://doi.org/10.1109/RFIC.2010.5477268","url":null,"abstract":"A 4–4.5 GHz receiver front-end consisting of a 35 dB voltage gain regenerative amplifier, ultra-narrowband RF filter and an envelope detector demodulator for FM-UWB communication is described in this paper. Implemented in 65 nm CMOS, the measured receiver sensitivity is −83 dBm at 100 kbps data rate with 15 dB output SNR (10−6 BER). The 0.3 mm2 test chip includes a 50 Ohm buffer amplifier to facilitate testing and consumes 2.2 mW (excluding buffer) from a 1 V supply.","PeriodicalId":269027,"journal":{"name":"2010 IEEE Radio Frequency Integrated Circuits Symposium","volume":"72 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126259319","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}