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23rd IEEE VLSI Test Symposium (VTS'05)最新文献

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Effective TARO pattern generation 有效的TARO模式生成
23rd IEEE VLSI Test Symposium (VTS'05) Pub Date : 2005-05-01 DOI: 10.1109/VTS.2005.43
I. Park, Ahmad A. Al-Yamani, E. McCluskey
{"title":"Effective TARO pattern generation","authors":"I. Park, Ahmad A. Al-Yamani, E. McCluskey","doi":"10.1109/VTS.2005.43","DOIUrl":"https://doi.org/10.1109/VTS.2005.43","url":null,"abstract":"TARO test patterns are transition fault test patterns that sensitize each transition fault to all of the outputs that can be reached from the fault location. We were not able to identify any ATPG tool that can generate TARO test patterns directly. This paper describes a technique to use an existing transition fault ATPG tool to efficiently generate TARO test patterns. This technique was used to generate TARO patterns for the ELF35 test chip. When these patterns were applied to the ELF35 chips, all of the defective chips were discovered (no test escapes).","PeriodicalId":268324,"journal":{"name":"23rd IEEE VLSI Test Symposium (VTS'05)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129501239","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 12
Constructive derivation of analog specification test criteria 模拟规范测试标准的建设性推导
23rd IEEE VLSI Test Symposium (VTS'05) Pub Date : 2005-05-01 DOI: 10.1109/VTS.2005.36
H. Stratigopoulos, Y. Makris
{"title":"Constructive derivation of analog specification test criteria","authors":"H. Stratigopoulos, Y. Makris","doi":"10.1109/VTS.2005.36","DOIUrl":"https://doi.org/10.1109/VTS.2005.36","url":null,"abstract":"We discuss the design of a neural system that learns to separate nominal from faulty instances of an analog circuit in a low dimensional measurement space. The key novelty of the proposed system is that it successively establishes a separation hypersurface of order that adapts to the intrinsic complexity of the problem. Thus, it performs excellent classification even in the presence of complex distributions. The test criterion for classifying a circuit is simply the location of its measurement pattern with respect to the separation hypersurface. Despite its simplicity, this criterion is, by construction, strongly correlated to the performance parameters of the circuit and does not rely on fault models.","PeriodicalId":268324,"journal":{"name":"23rd IEEE VLSI Test Symposium (VTS'05)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117291651","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
Towards an understanding of no trouble found devices 朝着理解无麻烦发现装置的方向前进
23rd IEEE VLSI Test Symposium (VTS'05) Pub Date : 2005-05-01 DOI: 10.1109/VTS.2005.86
Scott Davidson
{"title":"Towards an understanding of no trouble found devices","authors":"Scott Davidson","doi":"10.1109/VTS.2005.86","DOIUrl":"https://doi.org/10.1109/VTS.2005.86","url":null,"abstract":"This paper gives a model for understanding no trouble found (NTF) parts, including predictions of how many can be expected at different stages of a product life cycle, an understanding of when NTFs are of concern, and when they are to be expected. We also show how NTF rates can be used as a measure of process health.","PeriodicalId":268324,"journal":{"name":"23rd IEEE VLSI Test Symposium (VTS'05)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123748604","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 23
Hardware results demonstrating defect detection using power supply signal measurements 硬件结果演示使用电源信号测量缺陷检测
23rd IEEE VLSI Test Symposium (VTS'05) Pub Date : 2005-05-01 DOI: 10.1109/VTS.2005.47
D. Acharyya, J. Plusquellic
{"title":"Hardware results demonstrating defect detection using power supply signal measurements","authors":"D. Acharyya, J. Plusquellic","doi":"10.1109/VTS.2005.47","DOIUrl":"https://doi.org/10.1109/VTS.2005.47","url":null,"abstract":"The power supply transient signal (I/sub DDT/) method that we propose for defect detection analyzes regional signal variations introduced by defects at a set of power supply pads on the chip under test (CUT). The method is based on the comparison of the CUT with chips that are known to be defect free. A set of defect free chips are analyzed to establish a statistical metric that distinguishes between defect effects and process variation (defect free) effects. This paper presents hardware results that demonstrate the effectiveness of a novel geometry based defect detection technique using nine copies of a test chip. Eight chips are used as defect free chips to derive the statistical limits. Emulated defects are provoked in the ninth chip to evaluate the defect detection capabilities of the method.","PeriodicalId":268324,"journal":{"name":"23rd IEEE VLSI Test Symposium (VTS'05)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131364897","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 14
Measures to improve delay fault testing on low-cost testers - a case study 改进低成本测试仪延迟故障测试的措施 - 案例研究
23rd IEEE VLSI Test Symposium (VTS'05) Pub Date : 2005-05-01 DOI: 10.1109/VTS.2005.54
Matthias Beck, Olivier Barondeau, Frank Poehl, X. Lin, R. Press
{"title":"Measures to improve delay fault testing on low-cost testers - a case study","authors":"Matthias Beck, Olivier Barondeau, Frank Poehl, X. Lin, R. Press","doi":"10.1109/VTS.2005.54","DOIUrl":"https://doi.org/10.1109/VTS.2005.54","url":null,"abstract":"This paper addresses delay test for SOC devices on low-cost testers. The case study focuses on the at-speed testing for a state-of the-art microcontroller device by using an on-chip high-speed clock generator. The experimental results show that the simple on-chip high-speed clock generator is not sufficient to reach both high fault coverage and acceptable pattern count. Meanwhile, at-speed test constraints, required to enable the delay test on low cost testers, have a significant impact on test generation results. DFT techniques to increase fault coverage and to reduce pattern count are discussed.","PeriodicalId":268324,"journal":{"name":"23rd IEEE VLSI Test Symposium (VTS'05)","volume":"302 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129327689","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
At-speed transition fault testing with low speed scan enable 启用低速扫描的高速过渡故障测试
23rd IEEE VLSI Test Symposium (VTS'05) Pub Date : 2005-05-01 DOI: 10.1109/VTS.2005.31
N. Ahmed, C. Ravikumar, M. Tehranipoor, J. Plusquellic
{"title":"At-speed transition fault testing with low speed scan enable","authors":"N. Ahmed, C. Ravikumar, M. Tehranipoor, J. Plusquellic","doi":"10.1109/VTS.2005.31","DOIUrl":"https://doi.org/10.1109/VTS.2005.31","url":null,"abstract":"With today's design size in millions of gates and working frequency in gigahertz range, at-speed test is crucial. The launch-off-shift method has several advantages over the launch-off-capture but imposes strict requirements on transition fault testing due to at-speed scan enable signal. A novel scan-based at-speed test is proposed which generates multiple local fast scan enable signals. The scan enable control information is encapsulated in the test data and transferred during the scan operation. A new scan cell, referred to as last transition generator (LTG), is inserted in the scan chains to generate the fast local scan enable signal. The proposed technique is robust, practice-oriented and suitable for use in an industrial flow.","PeriodicalId":268324,"journal":{"name":"23rd IEEE VLSI Test Symposium (VTS'05)","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116369838","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 53
Synthesis of X-tolerant convolutional compactors 耐x卷积紧致器的合成
23rd IEEE VLSI Test Symposium (VTS'05) Pub Date : 2005-05-01 DOI: 10.1109/VTS.2005.81
J. Rajski, J. Tyszer
{"title":"Synthesis of X-tolerant convolutional compactors","authors":"J. Rajski, J. Tyszer","doi":"10.1109/VTS.2005.81","DOIUrl":"https://doi.org/10.1109/VTS.2005.81","url":null,"abstract":"The paper presents a very efficient method for synthesis of convolutional compactors capable of tolerating a number of unknown states in a single time frame while providing very high compaction ratios.","PeriodicalId":268324,"journal":{"name":"23rd IEEE VLSI Test Symposium (VTS'05)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124126635","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 33
Diagnosis of the failing component in RF receivers through adaptive full-path measurements 基于自适应全径测量的射频接收机故障诊断
23rd IEEE VLSI Test Symposium (VTS'05) Pub Date : 2005-05-01 DOI: 10.1109/VTS.2005.42
E. Acar, S. Ozev
{"title":"Diagnosis of the failing component in RF receivers through adaptive full-path measurements","authors":"E. Acar, S. Ozev","doi":"10.1109/VTS.2005.42","DOIUrl":"https://doi.org/10.1109/VTS.2005.42","url":null,"abstract":"Decreasing profit margins and time-to-market windows for radiofrequency transceivers, rule out the traditional component-based testing and diagnosis methods. Over the past few years, there has been a significant shift in the transceiver test methods towards full-path and loop-back testing. However, the benefits of path-based testing cannot be fully attained unless complimentary diagnosis methods can be developed. In this paper, we present an adaptive diagnosis methodology to identify the failing component in RF receivers. Once the fault type (hard fault or soft fault) is identified using eigensignature correlations, input signals are selected and ambiguity groups determined. A new input signal is applied based on the ambiguity groups until full diagnostic resolution is reached or test inputs are exhausted. While it is typically believed that partitioned parameters, such as the gain of an individual component, cannot be fully diagnosed, the inherently non-linear behavior of analog blocks results in distinguishable response patterns even for scalar parameters. Experimental results confirm that diagnosis using only path-based measurements is viable.","PeriodicalId":268324,"journal":{"name":"23rd IEEE VLSI Test Symposium (VTS'05)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115324494","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 16
A BIST scheme for FPGA interconnect delay faults FPGA互连延迟故障的一种BIST方案
23rd IEEE VLSI Test Symposium (VTS'05) Pub Date : 2005-05-01 DOI: 10.1109/VTS.2005.5
Chunyu Wang, J. Liou, Yen-Lin Peng, Chih-Tsun Huang, Cheng-Wen Wu
{"title":"A BIST scheme for FPGA interconnect delay faults","authors":"Chunyu Wang, J. Liou, Yen-Lin Peng, Chih-Tsun Huang, Cheng-Wen Wu","doi":"10.1109/VTS.2005.5","DOIUrl":"https://doi.org/10.1109/VTS.2005.5","url":null,"abstract":"In this paper, we propose a new BIST-based approach for testing FPGA interconnect delay faults. The BIST architecture utilizes the regularity of an FPGA by implementing small test circuits repetitively over FPGA's CLB arrays. Each test circuit targets a specific path and determine conformance of the path delay according to a test clock. With the target path configured as a loop back in the test circuit, test accuracy of the path delay can be increased with reduced effects from skews of the test clocks. Thus, this BIST has a higher delay fault coverage, since it is not necessary to apply guard bands for skews in test mode.","PeriodicalId":268324,"journal":{"name":"23rd IEEE VLSI Test Symposium (VTS'05)","volume":"61 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116569653","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 12
Low-cost alternate EVM test for wireless receiver systems 无线接收系统的低成本替代EVM测试
23rd IEEE VLSI Test Symposium (VTS'05) Pub Date : 2005-05-01 DOI: 10.1109/VTS.2005.53
Achintya Halder, A. Chatterjee
{"title":"Low-cost alternate EVM test for wireless receiver systems","authors":"Achintya Halder, A. Chatterjee","doi":"10.1109/VTS.2005.53","DOIUrl":"https://doi.org/10.1109/VTS.2005.53","url":null,"abstract":"In digital radio applications, error-vector-magnitude (EVM) is the primary specification which quantifies the performance of digital modulation implemented in silicon. Production testing of EVM incurs high cost of test instrumentation in automated test equipment (ATE). For EVM testing of wireless receivers, the ATE must include an RF transmitter having (1) the required digital modulation capability, (2) transmitter parameter configurability via test automation software and (3) higher performance and accuracy compared to the receiver-under-test. In this paper, an alternate test methodology for the EVM specification is proposed that eliminates the need for high cost RF sources with digital modulation capability. A sequence of multi-tones generated using low-cost RF sources is used as test stimuli. The EVM specification is computed (predicted) by analyzing the degradation of the test signal by the receiver modules (e.g. LNAs, mixers, filters) by means of the observed waveforms in the baseband. Simulation results are presented.","PeriodicalId":268324,"journal":{"name":"23rd IEEE VLSI Test Symposium (VTS'05)","volume":"130 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134458382","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 66
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