有效的TARO模式生成

23rd IEEE VLSI Test Symposium (VTS'05) Pub Date : 2005-05-01 DOI:10.1109/VTS.2005.43

I. Park, Ahmad A. Al-Yamani, E. McCluskey

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引用次数: 12

摘要

TARO测试模式是过渡故障测试模式，它将每个过渡故障敏感到从故障位置可以到达的所有输出。我们无法确定任何可以直接生成TARO测试模式的ATPG工具。本文介绍了一种利用已有的过渡故障ATPG工具高效生成TARO测试模式的技术。该技术用于生成ELF35测试芯片的TARO图案。当这些模式应用于ELF35芯片时，发现了所有有缺陷的芯片(没有测试逃逸)。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Effective TARO pattern generation

TARO test patterns are transition fault test patterns that sensitize each transition fault to all of the outputs that can be reached from the fault location. We were not able to identify any ATPG tool that can generate TARO test patterns directly. This paper describes a technique to use an existing transition fault ATPG tool to efficiently generate TARO test patterns. This technique was used to generate TARO patterns for the ELF35 test chip. When these patterns were applied to the ELF35 chips, all of the defective chips were discovered (no test escapes).

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23rd IEEE VLSI Test Symposium (VTS'05)

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