2014 IEEE International Conference on Semiconductor Electronics (ICSE2014)最新文献

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Top-down fabrication of silicon nanowire sensor using electron beam and optical mixed lithography 利用电子束和光学混合光刻技术自顶向下制造硅纳米线传感器
2014 IEEE International Conference on Semiconductor Electronics (ICSE2014) Pub Date : 2014-10-13 DOI: 10.1109/SMELEC.2014.6920796
S. Rahman, N. Yusof, M. Hamidon, R. M. Zawawi, U. Hashim
{"title":"Top-down fabrication of silicon nanowire sensor using electron beam and optical mixed lithography","authors":"S. Rahman, N. Yusof, M. Hamidon, R. M. Zawawi, U. Hashim","doi":"10.1109/SMELEC.2014.6920796","DOIUrl":"https://doi.org/10.1109/SMELEC.2014.6920796","url":null,"abstract":"The realization of reliable nanobiosensor devices requires the improvement of fabrication techniques to form the nanometer-sized structures and patterns, which were used to attach nano materials such as DNA for the device elements. This study demonstrates the sensitivity of silicon nanowires (SiNWs)as a sensing element in sensor application. Starting with silicon on insulator (SOI) material, the SiNWswith <;100nm in width were fabricated using electron beam lithography combined with conventional CMOS process. Different numbers of SiNWs which are single, 10 arrays of nanowires and 20 arrays of nanowires were developed. Subsequently, the two metal electrodes which are designated as source (S) and drain (D) were fabricated on top of individual SiNWs using optical lithography process. Optical and electrical characteristic have been proposed to verify the outcome of the fabricated structures. One major part is to observe the SiNWs optically in order to meet the nano-scale variation by using High Power Microscope (HPM) inspection and Field Emission Scanning Electron Microscope (FESEM) imaging. Finally, the samples will be tested electrically using I-V measurement system. The results show thatdevice with single SiNW with 60nm in width give the highest resistivity value due to surface to volume ratio.","PeriodicalId":268203,"journal":{"name":"2014 IEEE International Conference on Semiconductor Electronics (ICSE2014)","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116882444","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Numerical estimation of self-sputtering effect in ionized physical vapor deposition system 电离物理气相沉积系统自溅射效应的数值估计
2014 IEEE International Conference on Semiconductor Electronics (ICSE2014) Pub Date : 2014-10-13 DOI: 10.1109/SMELEC.2014.6920780
N. Nayan, J. Lias, M. Z. Sahdan, M. K. Ahmad, Lim Huey Sia, L. Wei, A. S. Abu Bakar, M. Rusop
{"title":"Numerical estimation of self-sputtering effect in ionized physical vapor deposition system","authors":"N. Nayan, J. Lias, M. Z. Sahdan, M. K. Ahmad, Lim Huey Sia, L. Wei, A. S. Abu Bakar, M. Rusop","doi":"10.1109/SMELEC.2014.6920780","DOIUrl":"https://doi.org/10.1109/SMELEC.2014.6920780","url":null,"abstract":"During the fabrication of ultra large scale integrated (ULSI) circuits, Ti and TiN thin films are used as diffusion seed and barrier layers in Cu metal contacts. They are often deposited using magnetron sputtering technique where energetic ions bombard the target surface to release the target material. In ionized physical vapor deposition (IPVD) system, the sputtered atoms are ionized in the plasma and thus accelerated into narrow trenches for Ti and TiN thin film fabrication. In IPVD, the density of ionized sputter Ti atom and Ar discharge gas may be at the same range. Therefore, the self-sputtering effect from ionized sputter Ti atoms is important. In the present work, the sputtering yields of Ti and TiN target materials with 100-800 eV at normal incident Ar and Ti ions are calculated. In addition, the influence of N ions in TiN sputtering is also considered. The simulation results are calculated from TRIM, which is a vectorized Monte Carlo code simulation of ion-surface interaction using a binary collision mode. The depth phenomenon of sputtered target incident is also discussed.","PeriodicalId":268203,"journal":{"name":"2014 IEEE International Conference on Semiconductor Electronics (ICSE2014)","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124631142","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Investigation on iodine flow rate in MEH-PPV: I-MWCNT nanocomposite thin film MEH-PPV: I-MWCNT纳米复合薄膜中碘流动速率的研究
2014 IEEE International Conference on Semiconductor Electronics (ICSE2014) Pub Date : 2014-10-13 DOI: 10.1109/SMELEC.2014.6920820
M. Sarah, M. Mudasir, S. S. Shariffudin, H. Hashim, M. Rusop
{"title":"Investigation on iodine flow rate in MEH-PPV: I-MWCNT nanocomposite thin film","authors":"M. Sarah, M. Mudasir, S. S. Shariffudin, H. Hashim, M. Rusop","doi":"10.1109/SMELEC.2014.6920820","DOIUrl":"https://doi.org/10.1109/SMELEC.2014.6920820","url":null,"abstract":"The effect of Iodine flow rate in nanocomposited MEH-PPV:I-MWCNT was investigated by means of electrical, optical and physical characterization. First, 120 mg of MWCNT was doped with 1g of Iodine using thermal chemical vapour deposition method (TCVD). The doping process was done for 1 hour with Iodine flow rate varied from 0.1, 0.3, 0.5, 0.7 and 0.9 l/min. On the other hand, 40 mg of MEH-PPV was stirred for 48 hours in tetrahydrofuran (THF). Next, the I-MWCNT was added to the solution to form nanocomposited MEH-PPV: I-MWCNT solution. The solution was then deposited on glass substrate using spin coating technique. The current-voltage (I-V) measurements were done in dark and under illumination. UV-Vis Spectrometer was used to measure the absorbance and transmittance. For physical properties, the characterizations were done using FESEM and Surface Profiler. From the I-V characteristic, thin film with Iodine flow rate 0.9 l/min gives the best result considering some response it gives towards light. Besides, the sample shows the highest photoconductivity with 2.82×10-3 S/cm. In optical properties, the thin film also gives value 0.89 unit of absorption spectra which is the highest value among other samples. The optimized flow rate will be used to fabricate an active layer of organic solar cell.","PeriodicalId":268203,"journal":{"name":"2014 IEEE International Conference on Semiconductor Electronics (ICSE2014)","volume":"30 8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126252025","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Annealing temperature effect on nanostructured TiO2 films 退火温度对纳米TiO2薄膜的影响
2014 IEEE International Conference on Semiconductor Electronics (ICSE2014) Pub Date : 2014-10-13 DOI: 10.1109/SMELEC.2014.6920882
I. H. Affendi, M. Sarah, M. Rusop
{"title":"Annealing temperature effect on nanostructured TiO2 films","authors":"I. H. Affendi, M. Sarah, M. Rusop","doi":"10.1109/SMELEC.2014.6920882","DOIUrl":"https://doi.org/10.1109/SMELEC.2014.6920882","url":null,"abstract":"The synthesization of TiO2 sol-gel, by using titanium dioxide nano powder as precursor. In the production of nanostructured TiO2, the annealing temperature for the film is differed to clarify the use of different temperature in annealing the film, the best temperature to get a good mobility in the current flow can be found. There are 7 samples with different drying temperature and different annealing temperature. The one with the highest IV characterization will be fabricated as thin film in the organic solar cell as the metal oxide film. As further discovered that the as-deposited without annealing sample have a quite thick film that it could not be characterized by Atomic Force Microscopy (AFM). The highest point of the current at 10 V in the IV graph is 500 C annealing temperature of 6.06E-9 A which then makes it the highest in conductivity at 3.37E-6 Sm-1. The current-voltage (I-V) measurement is used to study the electrical resistivity behaviour, hence the conductivity of the film to suit organic solar cell application.","PeriodicalId":268203,"journal":{"name":"2014 IEEE International Conference on Semiconductor Electronics (ICSE2014)","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126607823","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
SOI photodiode with surface plasmon antenna: From sensitivity enhancement to refractive index measurement for biosensing 表面等离子体天线的SOI光电二极管:从灵敏度增强到折射率测量用于生物传感
2014 IEEE International Conference on Semiconductor Electronics (ICSE2014) Pub Date : 2014-10-13 DOI: 10.1109/SMELEC.2014.6920779
H. Inokawa
{"title":"SOI photodiode with surface plasmon antenna: From sensitivity enhancement to refractive index measurement for biosensing","authors":"H. Inokawa","doi":"10.1109/SMELEC.2014.6920779","DOIUrl":"https://doi.org/10.1109/SMELEC.2014.6920779","url":null,"abstract":"Summary form only given. In order to enhance the performance and functionality of the pn-junction photodiode in silicon on insulator (SOI), metallic line-and-space (L/S) surface plasmon (SP) antenna is introduced. In case of the 100-nm-thick silicon, external quantum efficiency (QE) of the photodiode can be increased by nearly an order of magnitude. The antenna shows wavelength and polarization selectivities, and incident angle dependence, and the peak wavelength and the polarization angle can be tailored only by changing the layout design. This is especially beneficial for integrating a variety of photodiodes with different characteristics in a single chip. Wavelengths of the QE peaks for various L/S pitches and light incident angles were examined in detail, and it was suggested that the coupling between the diffracted light from the L/S and the propagation modes in the SOI slab waveguide caused the QE enhancement. Related to this operation mechanism, it was found that the photodiode could detect the refractive index of the medium around the SP antenna as the shift of the peak wavelength when the incident light was tilted. This may lead to the fluorescence-label-free biosensing, featuring simple optics and high throughput attained by the parallelism with a large number of integrated photodiodes. Consequently, a wider application of this photodiode can be expected along with the evolution of the SOI-based large-scale integrated circuits (LSIs).","PeriodicalId":268203,"journal":{"name":"2014 IEEE International Conference on Semiconductor Electronics (ICSE2014)","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126633506","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A low power 0.18μm CMOS technology integrating dual-slope analog-to digital converter 集成双斜率模数转换器的低功耗0.18μm CMOS技术
2014 IEEE International Conference on Semiconductor Electronics (ICSE2014) Pub Date : 2014-10-13 DOI: 10.1109/SMELEC.2014.6920861
I. Halim, N. Yusof, S. Hassan
{"title":"A low power 0.18μm CMOS technology integrating dual-slope analog-to digital converter","authors":"I. Halim, N. Yusof, S. Hassan","doi":"10.1109/SMELEC.2014.6920861","DOIUrl":"https://doi.org/10.1109/SMELEC.2014.6920861","url":null,"abstract":"In this paper, a 4-bit integrating dual slope analog-to digital converter (DS-ADC) is designed which consumes low power and simplicity but slow conversion time. The design utilizing a Silvaco Electronic Design Automation (SEDA) tools with an advanced 0.18μm CMOS Technology using 1.8V power supply. This integrating dual slope ADC contains five main components, which are switching, integrator, comparator, control logic and counter at which the integrator is realized with a two-stage operational amplifier (op-amp) that provides sufficient gain, ICMR and low power dissipation. Simulation confirms that the proposed DS-ADC architecture shows a power efficiency of 2.4739mW with 1.06μs conversion time.","PeriodicalId":268203,"journal":{"name":"2014 IEEE International Conference on Semiconductor Electronics (ICSE2014)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121918419","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Performance evaluation of dual-channel armchair graphene nanoribbon field-effect transistor 双通道扶手型石墨烯纳米带场效应晶体管的性能评价
2014 IEEE International Conference on Semiconductor Electronics (ICSE2014) Pub Date : 2014-10-13 DOI: 10.1109/SMELEC.2014.6920815
Adila Syaidatul Azman, Z. Johari, R. Ismail
{"title":"Performance evaluation of dual-channel armchair graphene nanoribbon field-effect transistor","authors":"Adila Syaidatul Azman, Z. Johari, R. Ismail","doi":"10.1109/SMELEC.2014.6920815","DOIUrl":"https://doi.org/10.1109/SMELEC.2014.6920815","url":null,"abstract":"Graphene has become a potential successor to silicon in electronic devices. In this paper, the performance of dual-channel armchair graphene nanoribbon field-effect transistor (AGNR FET) is investigated. Both physical and electrical properties of dual-channel AGNR FET are simulated using Atomistic Tool Kit from Quantum Wise. Their band structures and transmission spectra are analyzed. Current-voltage characteristic is then extracted and the performance of single and dual-channel AGNR FETs is compared. From the simulation, it is found that dual-channel AGNR FET exhibits significant improvement in ON current over two fold. Results obtained will give insight in the implementation of dual-channel AGNR FET for performance enhancement in future electronic devices.","PeriodicalId":268203,"journal":{"name":"2014 IEEE International Conference on Semiconductor Electronics (ICSE2014)","volume":"101 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115110617","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Dielectrophoretic characterization of array type microelectrodes 阵列型微电极的介电泳特性
2014 IEEE International Conference on Semiconductor Electronics (ICSE2014) Pub Date : 2014-10-13 DOI: 10.1109/SMELEC.2014.6920841
M. R. Buyong, Norazreen Abd Aziz, A. A. Hamzah, B. Majlis
{"title":"Dielectrophoretic characterization of array type microelectrodes","authors":"M. R. Buyong, Norazreen Abd Aziz, A. A. Hamzah, B. Majlis","doi":"10.1109/SMELEC.2014.6920841","DOIUrl":"https://doi.org/10.1109/SMELEC.2014.6920841","url":null,"abstract":"This research describes an investigation of nonuniform electric field for dielectrophoretic forces, FDEP application in particles manipulation. In an electrokinetics occurrence, a miniaturized array type of two poles microelectrodes has been simulated using engineered particle and tested using graphite metalloid particles. The particles can be attracted towards the regions of strong electric field depending upon the particles is more polarisable than the suspending medium. Dielectrophoresis offers the controllable, selective and accurate manipulation of target graphite metalloid particles. The surface area of graphite attracted to microelectrodes gradually increased starting from 4 seconds for 3412, 3845, and 3764 um2, hence 4589, 4465 and 4739 um2 at the 6 seconds mark and finally 5588, 5569 and 5644 um2 after 8 seconds for three different test run respectively. Further study of optimal FDEP behavior on the electric field distribution for three poles microelectrodes was characterized by finite element method, (FEM). The outcome, FDEP response is further improved by additional poles microelectrodes from top side, instead of side by side in term the strength and direction of electric and displacement field. Ultimately, the findings of this work is possible to contribute in medical sciences research for the enrichment of stem cell from bone narrow and peripheral blood form via integration DEP into a lab on a chip, DLOC concept application.","PeriodicalId":268203,"journal":{"name":"2014 IEEE International Conference on Semiconductor Electronics (ICSE2014)","volume":"105 7S 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124836882","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 14
Comparative study on 8T SRAM with different type of sense amplifier 不同类型感测放大器的8T SRAM的比较研究
2014 IEEE International Conference on Semiconductor Electronics (ICSE2014) Pub Date : 2014-10-13 DOI: 10.1109/SMELEC.2014.6920862
S. Hassan, Idalailah Dayah, I. Halim
{"title":"Comparative study on 8T SRAM with different type of sense amplifier","authors":"S. Hassan, Idalailah Dayah, I. Halim","doi":"10.1109/SMELEC.2014.6920862","DOIUrl":"https://doi.org/10.1109/SMELEC.2014.6920862","url":null,"abstract":"This paper presents the comparative study on 8T SRAM with different type of sense amplifier. These sense amplifiers are voltage-mode sense amplifier (VMSA) and current-mode sense amplifier (CMSA). The first objective of this research is to design the 8T SRAM and sense amplifier and the next objective is to identify which design has better performance in term of power, speed, stability and area. Sense amplifiers are one of the most critical circuits in the periphery of CMOS memories that plays an important role to reduce the overall sensing delay and voltage. Earlier voltage mode sense amplifiers sense the voltage difference at bit and bit lines bar but as the memory size increase the bit line and date line capacitances increases. The tools used for simulation is SILVACO EDA Gateway and SILVACO EDA Expert for layout using 0.18um technology. The results show that the CMSA has higher speed with lower delay, and low power dissipation than VMSA. But, VMSA has smaller cell area and higher noise margin than CMSA. CMSA is more suitable for high speed performance and low power circuitry and VMSA is best suited for stability and smaller design.","PeriodicalId":268203,"journal":{"name":"2014 IEEE International Conference on Semiconductor Electronics (ICSE2014)","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128343832","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 15
Effect of different tunnel diodes on the efficiency of multi-junction III-V solar cells 不同隧道二极管对多结III-V型太阳能电池效率的影响
2014 IEEE International Conference on Semiconductor Electronics (ICSE2014) Pub Date : 2014-10-13 DOI: 10.1109/SMELEC.2014.6920856
H. Yu, Hong-Quan Nguyen, Chen-Chen Chung, Ching-Hsiang Hsu, C. Hsiao, E. Chang
{"title":"Effect of different tunnel diodes on the efficiency of multi-junction III-V solar cells","authors":"H. Yu, Hong-Quan Nguyen, Chen-Chen Chung, Ching-Hsiang Hsu, C. Hsiao, E. Chang","doi":"10.1109/SMELEC.2014.6920856","DOIUrl":"https://doi.org/10.1109/SMELEC.2014.6920856","url":null,"abstract":"InGaP/GaAs dual-junction solar cells with different tunnel diodes (TDs) grown on misoriented GaAs substrates are investigated. It is found that the solar cells with P<sup>++</sup>-AlGaAs/N<sup>++</sup>-GaAs TDs grown on 10° off GaAs substrates show a higher external quantum efficiency (EQE) but also generate a higher peak current density (J<sub>peak</sub>) than the solar cells with P<sup>++</sup>-GaAs/N<sup>++</sup>-InGaP TDs grown on 10°off GaAs substrates. Furthermore, smooth surface (rms roughness: 1.54 Å) and sharp interface for the GaAs/Al<sub>0.3</sub>Ga<sub>0.7</sub>As TDs were obtained when the (100) tilted 10° off toward [111] GaAs substrate was used. The conversion efficiency of InGaP/GaAs dual-junction solar cell with N<sup>++</sup>-GaAs/P<sup>++</sup>-AlGaAs TD grown on the (100) tilted 10° off toward (111) GaAs substrate is close to 20%.","PeriodicalId":268203,"journal":{"name":"2014 IEEE International Conference on Semiconductor Electronics (ICSE2014)","volume":"86 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121651786","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
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