N. M. Saleh, B. Y. Lim, C. Voon, S. T. Ten, M. Derman, K. L. Foo, M. Arshad, U. Hashim
{"title":"Effects of ethanol in oxalic acid on the synthesis of porous anodic alumina","authors":"N. M. Saleh, B. Y. Lim, C. Voon, S. T. Ten, M. Derman, K. L. Foo, M. Arshad, U. Hashim","doi":"10.1109/SMELEC.2014.6920885","DOIUrl":"https://doi.org/10.1109/SMELEC.2014.6920885","url":null,"abstract":"Porous anodic alumina is a self-organizing porous material suitable as a template for obtaining nanostructured semiconductor materials. However, low temperature is generally used for the synthesis of porous anodic alumina. In this study, porous anodic alumina films were synthesized by a simple one-step anodizing technique at constant potential 40V using different volume percentage of ethanol in 0.5M oxalic acid at the temperatures of 25 °C. The current versus time transient was recorded by using Keithley sourcemeter. The morphology of the samples was viewed by a scanning electron microscopy. The current versus time transient decreased with the volume percent of ethanol, indicating reduction of growth rate of porous anodic alumina. Porous anodic alumina formed in oxalic acid without ethanol exhibit a complicated structure with irregular pore size and pore shape. Increasing volume percent of ethanol in the oxalic acid improved the pore size and shape. This is probably due to the cooling effect of the ethanol and prolonged time for pore organization. Typical morphology of porous anodic alumina can be formed by anodizing at 40 V at room temperature of 25 °C in 0.5 M oxalic acid with the addition of minimum of 30 volume percent of ethanol.","PeriodicalId":268203,"journal":{"name":"2014 IEEE International Conference on Semiconductor Electronics (ICSE2014)","volume":"97 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115355195","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
S. Johari, Nithiyah Tamilchelvan, M. Nor, M. M. Ramli, B. N. Taib, M. Mazalan, Y. Wahab
{"title":"The effect of softbaking temperature on SU-8 photoresist performance","authors":"S. Johari, Nithiyah Tamilchelvan, M. Nor, M. M. Ramli, B. N. Taib, M. Mazalan, Y. Wahab","doi":"10.1109/SMELEC.2014.6920899","DOIUrl":"https://doi.org/10.1109/SMELEC.2014.6920899","url":null,"abstract":"One of the steps required during the fabrication of SU-8 mold for soft lithography is softbaking, which is conducted after the deposition of the photoresist. The purpose of softbaking is to stabilize the resist film and eliminate any remaining solvent through evaporation. This ensures that the resist surface is non-sticking, hence avoiding debris when transferring the patterns later. In this paper, we investigate the effects of softbaking temperature on the polymerization of SU-8 photoresist. The significance of this work is to optimize the fabrication process involved in producing SU-8 mold structures with thickness of 30 μm. This project involves a series of experiments covering softbaking temperatures ranging from 45° to 115° C. Experiments results show that softbaking temperature of 85°C results in completely stick and crack free structures. By this, a huge improvement obtained if compared to the result of processing at the standard soft bake temperature of 95°C. The soft bake temperature should not be taken lightly while optimizing SU-8 processing because it has a big influence on the material properties and the lithographic performance of the resist.","PeriodicalId":268203,"journal":{"name":"2014 IEEE International Conference on Semiconductor Electronics (ICSE2014)","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124282193","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Synthesis and characterization of carbon nano structures on Gallium Phosphate","authors":"Aishah Fauthan, Z. Yunusa, M. Hamidon, B. Majlis","doi":"10.1109/SMELEC.2014.6920781","DOIUrl":"https://doi.org/10.1109/SMELEC.2014.6920781","url":null,"abstract":"Carbon nano structures were grown on Gallium Phosphate substrate by using Alcohol Catalytic Chemical Vapor Deposition (ACCVD) method. The aim of this paper is to study the structure and the morphology of the carbon nano structures growth on Gallium Phosphate. Gallium Phosphate is known as piezoelectric materials which are more stable and similar to quartz in its crystal structure. The ACCVD is chosen because of its simplicity and economical method for the growth of carbon nano structure. Mixture of ethanol and Iron Nitrate in a ratio of 1:25 was used as the catalyst to impregnate the carbon nano structures. The carbon nano structures were grown at 800oC. The ethanol liquid which was used as a carbon source was injected into the furnace tube with flow rate of 2.0 ml/min. The furnace was flowed by Argon gasses throughout the experiment. FE-SEM and EDX are used to investigate the morphology of the carbon structure. Finally Raman measurements have been performed and equipped with laser diode emitting at 632nm.","PeriodicalId":268203,"journal":{"name":"2014 IEEE International Conference on Semiconductor Electronics (ICSE2014)","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114789036","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Convergence of emerging technologies to address the challenges of the 21st century","authors":"A. M. Madni","doi":"10.1109/SMELEC.2014.6920774","DOIUrl":"https://doi.org/10.1109/SMELEC.2014.6920774","url":null,"abstract":"There are numerous \"Grand Challenges\" facing humanity that will have to be addressed by us as a global society in order to maintain our well-being from the standpoint of quality of life, healthcare, environment, energy needs, manufacturing efficiencies, etc., if we are to continue humanity's trajectory of progress. Traditional technologies based on classical disciplines and thought processes of the past several decades are no longer viable in addressing these challenges, and a new approach based on interdisciplinary thinking is necessary. Fortunately, numerous emerging technologies are advancing at an unimaginable rate and it is the convergence of these technologies that demonstrate the potential to have a major impact on our lives, businesses, government, society and our planet. These emerging technologies are establishing the basis for a new paradigm in the development and commercialization of next generation intelligent, miniaturized, highly robust complex systems. This lecture will address some of these major technologies and their applications including, intelligent sensors and wireless sensor networks, intelligent cars and smart highways, tele-health (wireless healthcare), micro-electromechanical systems (MEMS), nanotechnology, clean technology, robotics and automation, smart grid, and ultra high throughput and wide bandwidth instrumentation.","PeriodicalId":268203,"journal":{"name":"2014 IEEE International Conference on Semiconductor Electronics (ICSE2014)","volume":"86 7","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120858627","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
B. S. Lim, M. Arshad, N. Othman, M. Fathil, M. F. Fatin, U. Hashim
{"title":"The impact of channel doping in junctionless field effect transistor","authors":"B. S. Lim, M. Arshad, N. Othman, M. Fathil, M. F. Fatin, U. Hashim","doi":"10.1109/SMELEC.2014.6920808","DOIUrl":"https://doi.org/10.1109/SMELEC.2014.6920808","url":null,"abstract":"In this paper, we present the simple approach in study the impact of channel doping on the operation of the junctionless transistor transistor in 25 nm gate lengths through 2D-TCAD Sentaurus simulation tools. We increase the channel doping up to the level of doping source and drain, thus creating the junctionless phenomena between source and drain. The transistor parameters such as threshold voltage, transconductance, subthreshold slope, drain-induced barrier lowering are extracted. The impacts of low and high drain voltages are also considered. The higher the doping concentration the larger drain current can be produced, however the drawback is larger subthreshold slope is also obtained due to wider channel preventing fully-depletion.","PeriodicalId":268203,"journal":{"name":"2014 IEEE International Conference on Semiconductor Electronics (ICSE2014)","volume":"69 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124596049","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Wei-Ching Huang, Y. Wong, Kuan-Shin Liu, Chi-Feng Hsieh, E. Chang
{"title":"The effects of growth parameters on the electrical properties in InAlN/AlN/GaN high-electron-mobility transistors (HEMTs)","authors":"Wei-Ching Huang, Y. Wong, Kuan-Shin Liu, Chi-Feng Hsieh, E. Chang","doi":"10.1109/SMELEC.2014.6920907","DOIUrl":"https://doi.org/10.1109/SMELEC.2014.6920907","url":null,"abstract":"The electrical properties in the InAlN/AlN/GaN high electron mobility transistor grown by metal-organic vapor deposition (MOCVD) with different growth parameters were investigated in this study. We observed that two-dimensional electron gas (2DEG) channel was influenced by thickness of AlN spacer layer and a stable stage prior to the growth of AlN spacer layer. The TEM images showed the generation of dislocations at interface between AlN/GaN and InAlN/AlN with the thicker AlN spacer layer. These dislocations acted as electron scattering center and degraded the electron mobility in the 2DEG channel. Besides, a too long stable stage also appeared degradation in the electron mobility due to the etching effect of H2 gas. By optimizing growth parameters, the highest electron mobility of 890 cm2/V.s.","PeriodicalId":268203,"journal":{"name":"2014 IEEE International Conference on Semiconductor Electronics (ICSE2014)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128562506","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
M. Said, J. Yunas, Roer Ekapawinto, B. Majlis, B. Bais
{"title":"Synthesization of nickel nanoparticles embedded in SU8 polymer for electromagnetic actuator membrane","authors":"M. Said, J. Yunas, Roer Ekapawinto, B. Majlis, B. Bais","doi":"10.1109/SMELEC.2014.6920834","DOIUrl":"https://doi.org/10.1109/SMELEC.2014.6920834","url":null,"abstract":"A study of synthesization and magnetic properties of cured polymer composite on nickel (Ni) as an actuator membrane is prepared in this work. SU8 3050 polymer is used to mix with magnetic nanoparticles Ni to produce a hybrid material. The mixing process are done by using mechanical stirrer, ultrasonication and manually hand stirring. In this work an easy sol-gel method is selected to embed magnetic particles into the polymer matrix. Characterization of particle distribution is observed by metallurgical microscopy and scanning electron microscope (SEM). It is observed that the spreading of Ni particles inside the polymer chain are constant without clustering effects. Magnetization curves of each sample are traced at room temperature using vibration sample magnetometer (VSM). A good compromising magnetic properties with patternable high aspect ratio structures have been successfully fabricated using a standard MEMS process.","PeriodicalId":268203,"journal":{"name":"2014 IEEE International Conference on Semiconductor Electronics (ICSE2014)","volume":"97 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132858842","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Darushini Kunalan, Chee Lee Cheong, C. F. Chau, Azrul bin Ghazali
{"title":"Design of a 4-bit adder using reversible logic in quantum-dot cellular automata (QCA)","authors":"Darushini Kunalan, Chee Lee Cheong, C. F. Chau, Azrul bin Ghazali","doi":"10.1109/SMELEC.2014.6920795","DOIUrl":"https://doi.org/10.1109/SMELEC.2014.6920795","url":null,"abstract":"Both quantum-dot cellular automata (QCA) and reversible logic are emerging technologies that are promising alternatives to overcoming the scaling and heat dissipation issues, respectively, in the current CMOS designs. Here, the fundamentals of QCA and reversible logic are studied; the feasibility of incorporating reversible logic in QCA designs is also demonstrated. Based on two existing designs, an improved version of the reversible gates, namely the Feynman Gate and the Toffoli Gate, were implemented in QCA technology using QCADesigner. The proposed design of the QCA-based Feynman Gate is faster by ½ cycle as compared to the existing design; while the proposed Toffoli Gate has the same latency as the existing design but it is readily to be cascaded into a more complex design. A 4-bit ripple carry adder in QCA is then designed using the proposed Feynman and Toffoli gates to realize a reversible QCA full adder. This 4-bit QCA adder with reversible logic consists of 2030 QCA cells, has a latency of 7 clock cycles and 8 garbage outputs.","PeriodicalId":268203,"journal":{"name":"2014 IEEE International Conference on Semiconductor Electronics (ICSE2014)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123157785","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
R. Abu Bakar, M. Nazmi, Awatif Harun, N. Kamarozaman, N. Shaari, S. M. M. Kasim, S. H. Herman
{"title":"Switching behavior of lateral-structured zinc oxide-based memristive device","authors":"R. Abu Bakar, M. Nazmi, Awatif Harun, N. Kamarozaman, N. Shaari, S. M. M. Kasim, S. H. Herman","doi":"10.1109/SMELEC.2014.6920894","DOIUrl":"https://doi.org/10.1109/SMELEC.2014.6920894","url":null,"abstract":"Lateral-structured zinc oxide (ZnO) based memristive device was studied. The effect of oxide and electrode size variations on the switching behavior was investigated. The lateral structure was formed by depositing the metal electrodes at the right and left ends of a glass substrate. The ZnO thin films were deposited right at the center of the metal coated substrate using sol-gel spin coating technique. The oxide and electrode widths were varied. It was observed that using the smallest oxide width in the combination with wide electrode size resulted in better memristive behavior. The values of both on and off resistances (RON and ROFF) were found to be decreased as the width of the electrode increasing. The hysteresis curve on the other hand became wider with the increases of electrode width. The ROFF/RON ratio was calculated to be 1.044.","PeriodicalId":268203,"journal":{"name":"2014 IEEE International Conference on Semiconductor Electronics (ICSE2014)","volume":"336 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123333830","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
V. Retnasamy, Z. Sauli, R. Vairavan, S. Taniselass, H. Mamat
{"title":"high power LED heat dissipation simulation analysis via heat sink fin variation","authors":"V. Retnasamy, Z. Sauli, R. Vairavan, S. Taniselass, H. Mamat","doi":"10.1109/SMELEC.2014.6920813","DOIUrl":"https://doi.org/10.1109/SMELEC.2014.6920813","url":null,"abstract":"In this work, significance of heat sink fins numbers on the heat dissipation of single chip high power LED package was addressed. The investigation was carried out through simulation by utilizing Ansys version 11. In this work, the heat sink fin numbers were increased from 4 fins to 6 fins, 8 fins, 10 fins and 12 fins respectively. The heat dissipation were evaluated in terms of operating junction temperature, thermal resistance and von Mises stress of the LED chip. Results of the analysis showed that with the increment of heat sink fins, the surface area of the heat sink also increases which in turn reduces the junction temperature of the GaN chip.","PeriodicalId":268203,"journal":{"name":"2014 IEEE International Conference on Semiconductor Electronics (ICSE2014)","volume":"49 ","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120942347","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}