2009 22nd International Conference on VLSI Design最新文献

{"title":"Impact of Bias Voltage on Magnetic Inductance of Carbon Nanotube Interconnects","authors":"K. C. Narasimhamurthy, R. Paily","doi":"10.1109/VLSI.Design.2009.21","DOIUrl":"https://doi.org/10.1109/VLSI.Design.2009.21","url":null,"abstract":"Single-walled carbon nanotube (SWCNT) bundles have the potential to provide an attractive solution for the resistivity and electromigration problems faced by traditional copper interconnects. This paper discusses the impact of bias voltage variation on magnetic inductance of SWCNT bundle. The variation of bias voltage on inductance was ignored so far. The authors utilize existing models for SWCNT bundle for evaluation. There is a significant variation in inductance value within the available range of bias voltage. This study shows that the inductance change with respect to bias voltages is about 1% to 35% at different lengths of SWCNTs.","PeriodicalId":267121,"journal":{"name":"2009 22nd International Conference on VLSI Design","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-01-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122333036","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Floorplanning for Partial Reconfiguration in FPGAs","authors":"Pritha Banerjee, Megha Sangtani, S. Sur-Kolay","doi":"10.1109/VLSI.Design.2009.36","DOIUrl":"https://doi.org/10.1109/VLSI.Design.2009.36","url":null,"abstract":"Partial Reconfiguration on heterogeneous Field Programmable Gate Arrays (FPGA) with millions of gates yields better utilization of resources by swapping in and out the active modules of one or more applications at an instant of time. Given a schedule of sub-task instances with each instance having a netlist of active modules, a global floorplanning method is essential to reduce there configuration overhead by fixing the position and shapes of common modules across all instances, while optimizing the performance. Here we propose a global floorplan generation method to obtain same positions for the common modules across all instances such that the heterogeneous resource requirements of all modules in each instance are satisfied, and the total wirelength (HPWL) over all instances is minimal. We also provide experimental results in support.","PeriodicalId":267121,"journal":{"name":"2009 22nd International Conference on VLSI Design","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-01-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127356675","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Latency, Power and Performance Trade-Offs in Network-on-Chips by Link Microarchitecture Exploration","authors":"Basavaraj Talwar, Shailesh Kulkarni, B. Amrutur","doi":"10.1109/VLSI.Design.2009.55","DOIUrl":"https://doi.org/10.1109/VLSI.Design.2009.55","url":null,"abstract":"This paper presents a power, latency and throughput trade-off study on NoCs by varying microarchitectural (e.g. pipelining) and circuit level (e.g. frequency and voltage) parameters. We change pipelining depth, operating frequency and supply voltage for 3 example NoCs - 16 node 2D Torus, Tree network and Reduced 2D Torus. We use an in-house NoC exploration framework capable of topology generation and comparison using parameterized models of Routers and links developed in SystemC. The framework utilizes interconnect power and delay models from a low-level modelling tool called  Intacte[1]. We find that increased pipelining can actually reduce latency. We also find that there exists an optimal degree of pipelining which is the most energy efficient in terms of minimizing energy-delay product.","PeriodicalId":267121,"journal":{"name":"2009 22nd International Conference on VLSI Design","volume":"17 7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-01-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131713162","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Design Optimization and Automation for Secure Cryptographic Circuits","authors":"K. Lin, Yi Tang Chiu, Shan-Chien Fang","doi":"10.1109/VLSI.Design.2009.57","DOIUrl":"https://doi.org/10.1109/VLSI.Design.2009.57","url":null,"abstract":"Various logic design styles have been proposed to counteract DPA (Differential Power Analysis) attacks for secure cryptographic IC design. However, only a couple of papers addressed the automatic synthesis and optimization for these secure logic circuits. This paper attempts to identify common optimization issues in typical masking-based countermeasures. They include (1) constrained Reed-Muller (RM) logic minimization, (2) minimum decomposition of multi-input AND gates and (3) minimum number of mask bits used to randomize power consumption. An OFDD-based heuristic method is proposed to minimize the RM logic with emphasis on literal number. The latter two optimization problems are formulated as zero-one integer linear programming and graph coloring problems respectively. Based on these formulations and optimizations, an automated design flow for secure cryptographic IC design was implemented in C language.","PeriodicalId":267121,"journal":{"name":"2009 22nd International Conference on VLSI Design","volume":"180 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-01-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133401567","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Unified Challenges in Nano-CMOS High-Level Synthesis","authors":"S. Mohanty","doi":"10.1109/VLSI.Design.2009.124","DOIUrl":"https://doi.org/10.1109/VLSI.Design.2009.124","url":null,"abstract":"The challenges in nano-CMOS circuit design include the following: variability, leakage, power, thermals, reliability, and yield. This talk will focus on interdependent consideration of these challenges during high-level (aka architectural or behavioral) synthesis. The majority of the existing design techniques related to these challenges are at the device or logic level of circuit abstraction and few are at the architectural level, however, the research is full swing in this direction. At the architecture level, there are balanced degrees of freedom to vary design parameters and take fast and correct design decisions at an early phase of the design cycle without propagating the design errors to lower levels of circuit abstraction, where it is costly to correct them. In addition, designing at higher levels of abstraction is an efficient way to cope with complexity, facilitate design verification, and increase design reuse. For maximizing yield of circuit design in the presence of variability the designers can rely on pre- silicon or post-silicon techniques. The pre-silicon techniques are statistical optimization approaches of design phases that use statistical power, leakage, and timing analysis for design space exploration and maximize the parametric yield. A variety of approaches for scheduling, resource sharing, and module selection techniques have been proposed in current literature in this respect. The post-silicon techniques are approaches like adaptive body biasing and adaptive supply voltage which are used to tune the fabricated chips such that the circuit yield can be optimized. This talk will discuss all these techniques proposed in the context of HLS.","PeriodicalId":267121,"journal":{"name":"2009 22nd International Conference on VLSI Design","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-01-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131132341","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"WOR-BIST: A Complete Test Solution for Designs Meeting Power, Area and Performance Requirements","authors":"Chunhua Yao, K. Saluja, Abhishek A. Sinkar","doi":"10.1109/VLSI.Design.2009.74","DOIUrl":"https://doi.org/10.1109/VLSI.Design.2009.74","url":null,"abstract":"A complete Built-In Self-Test (BIST) solution based on word oriented Random Access Scan architecture (WOR-BIST), is proposed. Our WOR-BIST scheme reduces the test power consumption significantly due to reduced switching activity during scan operations. We also provide a greedy algorithm to reduce the test data volume and test application time. We performed logic simulation of the test vectors to show its impact on the average and peak power during testing. We implemented the scheme to demonstrate its impact on the chip area and timing performance. Application of our scheme to large ISCAS and ITC benchmark circuits shows that our scheme is superior in area, power and performance to the conventional multiple serial scan.","PeriodicalId":267121,"journal":{"name":"2009 22nd International Conference on VLSI Design","volume":"201 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-01-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116157766","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Negative Feedback System and Circuit Design","authors":"N. Krishnapura, S. Pavan","doi":"10.1109/VLSI.Design.2009.116","DOIUrl":"https://doi.org/10.1109/VLSI.Design.2009.116","url":null,"abstract":"The negative feedback amplifier structure using an ideal integrator is derived. The time domain and frequency domain descriptions of the integrator are discussed. The response of the negative feedback amplifier in the time and frequency domains is analyzed. From these general conclusions are drawn about the behavior of negative feedback amplifiers. The ideal integrator is realized using controlled sources and passive elements. This realization clearly shows the cause for finite dc gain in real opamps. The effects of finite dc gain are analyzed. Relationships between amplifier specifications such as speed and accuracy and opamp parameters such as unity gain frequency and dc gain are derived. Methods of increasing the dc gain to improve accuracy are discussed. These lead to multistage amplifiers. The response of such systems in time and frequency domains are analyzed. It is shown that multistage amplifiers are potentially unstable. Stability conditions for negative feedback systems are discussed. The gain around the negative feedback loop is computed. The significance of loop gain is illustrated. Stability criteria related to the loop gain such as phase margin and Nyquist’s criterion are discussed. Frequently used criteria such as phase margin are clarified. Multistage amplifiers are essential for realizing high accuracy. Different techniques of realizing high gains while retaining stability-increasing the output resistance, miller compensation, and feedforward compensation are shown. There are various opamp architectures: folded/telescopic cascode; two stage miller compensated; feedforward compensated; and three stage. The design procedures for the two stage miller compensated opamp, the feedforward compensated opamp, and the three stage opamp are shown. These opamps will be compared in terms of their performance parameters-bandwidth, noise, power dissipation, slew rate, output swing. The design of a 350MHz bandwidth continuous-time active-RC filter using feedforward compensated opamps is shown. Measurement results from chips designed at IIT Madras illustrate the benefits of the feed-forward opamp architecture for low power applications. The design details of a three stage opamp with a DC gain exceeding 100dB is shown. The constraints on the design of different stages are evaluated. Simulation results of the opamp illustrate its suitability for a high precision application.","PeriodicalId":267121,"journal":{"name":"2009 22nd International Conference on VLSI Design","volume":"98 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-01-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124687759","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Computational Lithography - Moore Bang for your Buck","authors":"Vivek Singh","doi":"10.1109/VLSI.Design.2009.106","DOIUrl":"https://doi.org/10.1109/VLSI.Design.2009.106","url":null,"abstract":"There have been many pronouncements about the slowing down of Moore’s Law. Human enterprise, however, has managed to disprove these dim prophecies by producing ingenious solutions on a regular basis, to allow Moore’s Law to continue its unabated march. Many of these solutions are coming from the growing field of Computational Lithography. Generally speaking, Computational Lithography comprises a broad set of techniques that use physics-based calculations to eke out more lithographic performance from today’s steppers than they were originally designed for. Given the extraordinary cost of lithography tools and the fact that economics drives Moore’s Law as much as physics, this boost in IC affordability is a key driver of innovations in Computational Lithography. One such innovation is Pixelated Phase Mask technology. This technology was created to address the problem caused by the growing gap between the lithography wavelength and the feature sizes patterned with it. As this gap has increased, the quality of the image has deteriorated. About a decade ago, Optical Proximity Correction was introduced to bridge this gap, but as this gap continued to increase, one could not rely on the same basic set of techniques to maintain image quality. We sought to alleviate this problem by introducing additional degrees of freedom within the mask. The resulting Pixelated Phase Mask technology will be described in this paper, as an example of how Computational Lithography can contribute to affordable scaling and design productivity.","PeriodicalId":267121,"journal":{"name":"2009 22nd International Conference on VLSI Design","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-01-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125975299","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Accelerating Embedded System Design","authors":"Techonline","doi":"10.1109/VLSI.Design.2009.110","DOIUrl":"https://doi.org/10.1109/VLSI.Design.2009.110","url":null,"abstract":"Process for the production of optically-active di-[3-chloro-2-oxy-propyltrimethylammonium]-tartrate. Racemic 3-chloro-2-oxy-propyltrimethylammonium-chloride is converted by racemate resolution with optically-active tartaric acid into the optically-active di-[3-chloro-2-oxy-propyltrimethylammonium]-tartrate. Such optically-active tartrate compound is dissociated in tartaric acid to optically-active 3-chloro-2-oxy-propyltrimethylammonium-chloride and the latter is converted with inorganic cyanides. From the product, the production of optically-active carnitine nitrile chloride can be achieved.","PeriodicalId":267121,"journal":{"name":"2009 22nd International Conference on VLSI Design","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-01-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117021904","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A New Hardware Routing Accelerator for Multi-Terminal Nets","authors":"K. Fatima, R. Rao","doi":"10.1109/VLSI.Design.2009.44","DOIUrl":"https://doi.org/10.1109/VLSI.Design.2009.44","url":null,"abstract":"This paper presents a new parallel processing wire routing machine, which finds a quasi-minimum Steiner tree for multi-point connections in a VLSI chip. A hardware implementation with concurrent time-multiplexed wavefront propagation from all terminals of a net is described. The new design requires fewer clock cycles to find the shortest path than the existing parallel routing algorithms. The time-multiplexed mode optimizes the number of interconnections. An RTL implementation has been developed in VHDL and the algorithm has been successfully tested for a prototype 4 × 4 and 8 × 8 single layer grid on an FPGA. The feasibility of the algorithm for larger size grid and nets with higher degree is demonstrated.","PeriodicalId":267121,"journal":{"name":"2009 22nd International Conference on VLSI Design","volume":"59 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-01-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121542093","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}