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2019 IEEE International Workshop on Future Computing (IWOFC最新文献

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Sub-harmonic Injection Locking Memristor-based Oscillator Arrays Used for Pattern Recognition 用于模式识别的基于子谐波注入锁定忆阻器的振荡器阵列
2019 IEEE International Workshop on Future Computing (IWOFC Pub Date : 2019-12-01 DOI: 10.1109/IWOFC48002.2019.9078470
Yubing Xu, Bo Wang
{"title":"Sub-harmonic Injection Locking Memristor-based Oscillator Arrays Used for Pattern Recognition","authors":"Yubing Xu, Bo Wang","doi":"10.1109/IWOFC48002.2019.9078470","DOIUrl":"https://doi.org/10.1109/IWOFC48002.2019.9078470","url":null,"abstract":"Oscillatory neural network (ONN) is a promising computing architecture that can realize pattern recognition or other intellectual applications in real time. Emerging memristor-based oscillator provides a good choice as building block and corresponding phase behavioral model can accelerate simulation for about 40 times comparing to transistor level simulation. However, phase unlocking due to the frequency detuning after recognition is prominent in memristor-based traditional ONN architecture. With such problem, phase deviation cannot be locked and the correct recognized image fails to be continuously presented after synchronization. In this paper, a novel sub-harmonic injection locking (SHIL) memristor-based ONN is proposed to handle this problem. Energy function is used to give a deep insight into our method. Simulation both in MATLAB and Cadence shows a consistent frequency, i.e., constant phase differences. The results of error standard deviation of recognized patterns reduce 80, 36 and 192 times respectively in three representative cases.","PeriodicalId":266774,"journal":{"name":"2019 IEEE International Workshop on Future Computing (IWOFC","volume":"78 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115763764","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Optimization Strategy for Accelerating Multi-Bit Resistive Weight Programming on the RRAM Array 加速RRAM阵列上多位电阻权编程的优化策略
2019 IEEE International Workshop on Future Computing (IWOFC Pub Date : 2019-12-01 DOI: 10.1109/IWOFC48002.2019.9078447
Junren Chen, Huaqiang Wu, B. Gao, Jianshi Tang, Wenqiang Zhang, H. Qian
{"title":"Optimization Strategy for Accelerating Multi-Bit Resistive Weight Programming on the RRAM Array","authors":"Junren Chen, Huaqiang Wu, B. Gao, Jianshi Tang, Wenqiang Zhang, H. Qian","doi":"10.1109/IWOFC48002.2019.9078447","DOIUrl":"https://doi.org/10.1109/IWOFC48002.2019.9078447","url":null,"abstract":"To program the RRAM cells as multi-bit synaptic weights is attractive for neuromorphic computing. In this work, we experimentally studied the optimization strategy for accelerating multi-bit resistive weight programming at the array level, which is different from standalone single cells. The results suggest that a certain degree of overshoot on part of cells can improve overall programming speed. But excessive overshooting would reduce the programming success rate. With an optimized conductance tuning step size to program 4 bit/cell on the array, a ~5× speedup is achieved compared to traditional optimized ISPP scheme which is based on standalone single cells, and a high 99.94% overall success rate is experimentally realized when mapping a grayscale image on a 160Kb RRAM array with 4-bit precision. Moreover, the statistics indicate that a customized conductance tuning step size can be designed for individual target conductance levels to achieve the best performance with the fastest programming and a high programming success rate.","PeriodicalId":266774,"journal":{"name":"2019 IEEE International Workshop on Future Computing (IWOFC","volume":"101 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126620408","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Pulsed Operation and Low-energy Consumption Characteristic on HfON RRAM Devices as Electronic Synapse 作为电子突触的HfON RRAM器件的脉冲操作和低能耗特性
2019 IEEE International Workshop on Future Computing (IWOFC Pub Date : 2019-12-01 DOI: 10.1109/IWOFC48002.2019.9078438
Yuechi Ma, Ao Yu, Yaping Zhang, Zehao Wang, Xiangxiang Ding, Yulin Feng, Lifeng Liu
{"title":"Pulsed Operation and Low-energy Consumption Characteristic on HfON RRAM Devices as Electronic Synapse","authors":"Yuechi Ma, Ao Yu, Yaping Zhang, Zehao Wang, Xiangxiang Ding, Yulin Feng, Lifeng Liu","doi":"10.1109/IWOFC48002.2019.9078438","DOIUrl":"https://doi.org/10.1109/IWOFC48002.2019.9078438","url":null,"abstract":"In this work, HfON-based resistive random-access memory (RRAM) device was fabricated to investigate the low-energy consumption characteristic for electronic synapse application. A new pulse operation scheme was proposed to tune the resistance states of RRAM by applying variable pulse voltage amplitude and pulse width. The resistance change range can be larger than 1000. The effect of growth conditions with different nitrogen/oxygen ratio on switching energy consumption is also studied. It indicates that higher nitrogen/oxygen ratio in HfON layer is beneficial to the reduction of pulse switching energy consumption.","PeriodicalId":266774,"journal":{"name":"2019 IEEE International Workshop on Future Computing (IWOFC","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130552980","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Instability changes the MAGIC NAND gate to the NOR gate 不稳定性改变MAGIC NAND门为NOR门
2019 IEEE International Workshop on Future Computing (IWOFC Pub Date : 2019-12-01 DOI: 10.1109/IWOFC48002.2019.9078441
Xi Zhu, Hongchang Long, Zhiwei Li, Hui Xu, Haijun Liu, Qingjiang Li
{"title":"Instability changes the MAGIC NAND gate to the NOR gate","authors":"Xi Zhu, Hongchang Long, Zhiwei Li, Hui Xu, Haijun Liu, Qingjiang Li","doi":"10.1109/IWOFC48002.2019.9078441","DOIUrl":"https://doi.org/10.1109/IWOFC48002.2019.9078441","url":null,"abstract":"Memristor-based stateful logic demonstrates a method of in-memory computing, which is a promising way to overcome the data-transfer bottleneck in the current von Neumann computer architecture. However, due to the instability, the memristor device exhibits an inherent stochastic switching behavior especially when the applied voltage is in the switching range of unsafe writing. In such case, the delicate design of stateful memristor gates could suffer the reliability problem. Here, such unsafe writing impacts on the memristor-based logic operation is systematically analyzed. Through establishing the Markov chain model of unsafe writing effects, we deduce the mathematical relationship between the memristor-aided logic (MAGIC) gate reliability and switching probability. It reveals that unsafe writing with enough operation time would make the MAGIC NAND gate converge to always NOR logic. The best operation time for the unsafe write is then proposed to improve the probability of right logic function and avoid the undesired logic result, which is demonstrated with simulation.","PeriodicalId":266774,"journal":{"name":"2019 IEEE International Workshop on Future Computing (IWOFC","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131551808","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A Novel Homeostasis Method to Improve the Learning Efficiency of Spiking Neural Networks 一种提高脉冲神经网络学习效率的动态平衡新方法
2019 IEEE International Workshop on Future Computing (IWOFC Pub Date : 2019-12-01 DOI: 10.1109/IWOFC48002.2019.9078442
Lianhua Qu, Lei Wang, Shuo Tian, Ziyang Kang, Shiming Li, Weixia Xu
{"title":"A Novel Homeostasis Method to Improve the Learning Efficiency of Spiking Neural Networks","authors":"Lianhua Qu, Lei Wang, Shuo Tian, Ziyang Kang, Shiming Li, Weixia Xu","doi":"10.1109/IWOFC48002.2019.9078442","DOIUrl":"https://doi.org/10.1109/IWOFC48002.2019.9078442","url":null,"abstract":"Spiking neural networks (SNNs) trained by spike timing dependent plasticity (STDP) is a promising computing paradigm for unsupervised artificial intelligence systems. During the learning procedure of SNNs trained by STDP, homeostasis method is always implemented to mitigate the inhomogeneity induced by inputs and initial synapse weights. If homeostasis is not achieved effectively, the learning efficiency will be affected due to unbalanced training of neurons in the same layer. In this paper, we propose a novel homeostasis method and carry out software simulations to evaluate the learning efficiency and performance of the proposed method compared with two classical SNN learning algorithms. Simulation results on the task of digital recognition of MNIST dataset show that, our proposed method can achieve a ~2 times higher learning efficiency while maintaining comparable performance.","PeriodicalId":266774,"journal":{"name":"2019 IEEE International Workshop on Future Computing (IWOFC","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133710433","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
The Impact of Non-linear NVM Devices on In-Memory Computing 非线性NVM设备对内存计算的影响
2019 IEEE International Workshop on Future Computing (IWOFC Pub Date : 2019-12-01 DOI: 10.1109/IWOFC48002.2019.9078468
Sai Zhang, Zongdong Dai, R. Xiao, Haibin Shen, Kejie Huang
{"title":"The Impact of Non-linear NVM Devices on In-Memory Computing","authors":"Sai Zhang, Zongdong Dai, R. Xiao, Haibin Shen, Kejie Huang","doi":"10.1109/IWOFC48002.2019.9078468","DOIUrl":"https://doi.org/10.1109/IWOFC48002.2019.9078468","url":null,"abstract":"Deep learning has significantly improved the accuracy of large-scale visual/auditory recognition and classification tasks, at the cost of ever-increasing computational resource and storage capacity in hardware. As a result, the data communication between the computing and storage units has been the bottleneck in Artificial Intelligence (AI) computation. The emerging resistive NVMs based in-memory computing architectures have been considered at the promising solution scheme to address the abovementioned issue. However, the non-linearity of the NVM devices has a significant impact on the computing accuracy. In this paper, a non-linear RRAM is modelled and implemented in various in-memory computing architectures. The results show severe accuracy losses caused by the non-linear reading/writing property, mismatch, uncertainty, etc. Several promising solutions are also discussed in this paper.","PeriodicalId":266774,"journal":{"name":"2019 IEEE International Workshop on Future Computing (IWOFC","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132529475","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
MAGIC NAND within NOR gate 魔法非门在我的门内
2019 IEEE International Workshop on Future Computing (IWOFC Pub Date : 2019-12-01 DOI: 10.1109/IWOFC48002.2019.9078439
Hongchang Long, Xi Zhu, Zhiwei Li, Jietao Diao, Haijun Liu, Qingjiang Li
{"title":"MAGIC NAND within NOR gate","authors":"Hongchang Long, Xi Zhu, Zhiwei Li, Jietao Diao, Haijun Liu, Qingjiang Li","doi":"10.1109/IWOFC48002.2019.9078439","DOIUrl":"https://doi.org/10.1109/IWOFC48002.2019.9078439","url":null,"abstract":"In-memory computing based on memristor has attracted significant interest for breaking the von Neumann bottleneck and developing high-efficient computing systems. Memristor-based logic gate is one of the most important part to achieve our goals. Recently, there are many methods which have been presented to achieve Boolean functions. Such as material implication (IMPLY) and memristor-aided logic (MAGIC). MAGIC NAND gate can be used as a standalone logic which is not placed within a crossbar array. However, it's unavoidable to describe it within a crossbar array in order to design more circuits which can achieve more functions. So we use a 4*3 array which consists of memristors and transistors (1T1R) to simulate MAGIC NAND gate within a crossbar array. And we deduce the mathematical relationship between the applied voltage and the threshold voltage. Furthermore, we have verified NAND logic within the array and implemented vector NAND computation.","PeriodicalId":266774,"journal":{"name":"2019 IEEE International Workshop on Future Computing (IWOFC","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121585100","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Low-Power Resistive Switching Characteristics in TiN/TaON/SiO2/Pt RRAM devices for Neuromorphic Applications 神经形态应用TiN/TaON/SiO2/Pt RRAM器件的低功耗电阻开关特性
2019 IEEE International Workshop on Future Computing (IWOFC Pub Date : 2019-12-01 DOI: 10.1109/IWOFC48002.2019.9078471
Ao Yu, Yuechi Ma, Zehao Wang, Xiangxiang Ding, Yulin Feng, Lifeng Liu
{"title":"Low-Power Resistive Switching Characteristics in TiN/TaON/SiO2/Pt RRAM devices for Neuromorphic Applications","authors":"Ao Yu, Yuechi Ma, Zehao Wang, Xiangxiang Ding, Yulin Feng, Lifeng Liu","doi":"10.1109/IWOFC48002.2019.9078471","DOIUrl":"https://doi.org/10.1109/IWOFC48002.2019.9078471","url":null,"abstract":"In this work, the TiN/TaON/SiO2/Pt and TiN/TaON/Pt RRAM devices are fabricated and investigated. Compared with the TiN/TaON/Pt control device, TiN/TaON/SiO2/Pt RRAM devices with inserted SiO2 thin film show larger (x10) resistive window at the set compliance current of 1mA. TiN/TaON/SiO2/Pt RRAM devices show low-power resistive switching characteristic with set power of nearly 28.5µW (5.7V 5µA) and reset power of nearly 5.4µW (5.4V 1µA). Endurance characteristic with low-power resistive switching over 106 is demonstrated. The inserted SiO2 thin film may play the role of current limiting layer to achieve the low-power resistive switching characteristics in TiN/TaON/SiO2/Pt RRAM devices.","PeriodicalId":266774,"journal":{"name":"2019 IEEE International Workshop on Future Computing (IWOFC","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125781951","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Hardware Implementation of Softmax Function Based on Piecewise LUT 基于分段LUT的Softmax函数的硬件实现
2019 IEEE International Workshop on Future Computing (IWOFC Pub Date : 2019-12-01 DOI: 10.1109/IWOFC48002.2019.9078446
Xiao Dong, Xiaolei Zhu, De Ma
{"title":"Hardware Implementation of Softmax Function Based on Piecewise LUT","authors":"Xiao Dong, Xiaolei Zhu, De Ma","doi":"10.1109/IWOFC48002.2019.9078446","DOIUrl":"https://doi.org/10.1109/IWOFC48002.2019.9078446","url":null,"abstract":"Deep neural networks (DNN) achieve great results in many fields. While softmax function is widely used in DNN, how to implement it on hardware considering the accuracy, speed, area, and power, is a critical issue. This paper proposes a piecewise exponential lookup table (LUT) method, which reduces the LUT size of the exponential function in DNN's softmax layer. The experiment results show that the hardware using this method consumes less area and power resources than the previous work. The experiment input has a wide range and high accuracy, the absolute error of the calculation result is up to 4.5×10−6. The experiment results prove the proposed design is suitable for the softmax layer in most hardware implementation of DNN.","PeriodicalId":266774,"journal":{"name":"2019 IEEE International Workshop on Future Computing (IWOFC","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121902500","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
An 8-bit RRAM based Multiplier for Hybrid Memory Computing 一种用于混合内存计算的8位RRAM乘法器
2019 IEEE International Workshop on Future Computing (IWOFC Pub Date : 2019-12-01 DOI: 10.1109/IWOFC48002.2019.9078444
Xuan Zhou, Xiaolei Zhu, Bing Chen, Yi Zhao, Chengjie Fu
{"title":"An 8-bit RRAM based Multiplier for Hybrid Memory Computing","authors":"Xuan Zhou, Xiaolei Zhu, Bing Chen, Yi Zhao, Chengjie Fu","doi":"10.1109/IWOFC48002.2019.9078444","DOIUrl":"https://doi.org/10.1109/IWOFC48002.2019.9078444","url":null,"abstract":"Hybrid-memory computing can reconcile the speed of in-memory computing and the power of near-memory. An RRAM based multiplier for hybrid-memory computing is proposed to balance the efficiency and flexibility. It is implemented in standard RRAM model and 65nm CMOS technology. The simulation results show that the proposed RRAM based multiplier achieves a calculation speed of 1.6us and 1.32 mW from 1V power supply.","PeriodicalId":266774,"journal":{"name":"2019 IEEE International Workshop on Future Computing (IWOFC","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126996742","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
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