Xuan Zhou, Xiaolei Zhu, Bing Chen, Yi Zhao, Chengjie Fu
{"title":"一种用于混合内存计算的8位RRAM乘法器","authors":"Xuan Zhou, Xiaolei Zhu, Bing Chen, Yi Zhao, Chengjie Fu","doi":"10.1109/IWOFC48002.2019.9078444","DOIUrl":null,"url":null,"abstract":"Hybrid-memory computing can reconcile the speed of in-memory computing and the power of near-memory. An RRAM based multiplier for hybrid-memory computing is proposed to balance the efficiency and flexibility. It is implemented in standard RRAM model and 65nm CMOS technology. The simulation results show that the proposed RRAM based multiplier achieves a calculation speed of 1.6us and 1.32 mW from 1V power supply.","PeriodicalId":266774,"journal":{"name":"2019 IEEE International Workshop on Future Computing (IWOFC","volume":"8 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2019-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"An 8-bit RRAM based Multiplier for Hybrid Memory Computing\",\"authors\":\"Xuan Zhou, Xiaolei Zhu, Bing Chen, Yi Zhao, Chengjie Fu\",\"doi\":\"10.1109/IWOFC48002.2019.9078444\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Hybrid-memory computing can reconcile the speed of in-memory computing and the power of near-memory. An RRAM based multiplier for hybrid-memory computing is proposed to balance the efficiency and flexibility. It is implemented in standard RRAM model and 65nm CMOS technology. The simulation results show that the proposed RRAM based multiplier achieves a calculation speed of 1.6us and 1.32 mW from 1V power supply.\",\"PeriodicalId\":266774,\"journal\":{\"name\":\"2019 IEEE International Workshop on Future Computing (IWOFC\",\"volume\":\"8 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2019-12-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2019 IEEE International Workshop on Future Computing (IWOFC\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/IWOFC48002.2019.9078444\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2019 IEEE International Workshop on Future Computing (IWOFC","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IWOFC48002.2019.9078444","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
An 8-bit RRAM based Multiplier for Hybrid Memory Computing
Hybrid-memory computing can reconcile the speed of in-memory computing and the power of near-memory. An RRAM based multiplier for hybrid-memory computing is proposed to balance the efficiency and flexibility. It is implemented in standard RRAM model and 65nm CMOS technology. The simulation results show that the proposed RRAM based multiplier achieves a calculation speed of 1.6us and 1.32 mW from 1V power supply.