Optimization Strategy for Accelerating Multi-Bit Resistive Weight Programming on the RRAM Array

Abstract

To program the RRAM cells as multi-bit synaptic weights is attractive for neuromorphic computing. In this work, we experimentally studied the optimization strategy for accelerating multi-bit resistive weight programming at the array level, which is different from standalone single cells. The results suggest that a certain degree of overshoot on part of cells can improve overall programming speed. But excessive overshooting would reduce the programming success rate. With an optimized conductance tuning step size to program 4 bit/cell on the array, a ~5× speedup is achieved compared to traditional optimized ISPP scheme which is based on standalone single cells, and a high 99.94% overall success rate is experimentally realized when mapping a grayscale image on a 160Kb RRAM array with 4-bit precision. Moreover, the statistics indicate that a customized conductance tuning step size can be designed for individual target conductance levels to achieve the best performance with the fastest programming and a high programming success rate.