7th International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC)最新文献

Translating Java for resource constrained embedded systems 为资源受限的嵌入式系统翻译Java

7th International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC) Pub Date : 2012-07-09 DOI: 10.1109/ReCoSoC.2012.6322868

G. Plumbridge, N. Audsley

{"title":"Translating Java for resource constrained embedded systems","authors":"G. Plumbridge, N. Audsley","doi":"10.1109/ReCoSoC.2012.6322868","DOIUrl":"https://doi.org/10.1109/ReCoSoC.2012.6322868","url":null,"abstract":"This paper discusses a strategy for translating the Java programming language to a form that is suitable for execution on resource limited embedded systems such as softcore processors in FPGAs, Network-on-Chip nodes and microcontrollers. The translation strategy prioritises the minimisation of runtime memory usage, generated code size, and suitability for a wide range of small architectures over other desirable goals such as execution speed and strict adherence to the Java standard. The translation procedure, or Concrete Hardware Implementation of a software application first converts the application's compiled Java class files to a self-contained intermediate representation conducive to optimisation and refactoring. The intermediate format is then serialised into a programming language compilable to the target architecture. This paper presents techniques for analysing whole Java applications, translating Java methods and building a stand-alone translated application with the same functional behaviour as the original Java. An example C-code generator is described and evaluated against similar previous approaches. An existing benchmark application, JavaBenchEmbedded, is demonstrated to require less than 30KiB of program code and 16KiB of runtime heap memory when executing on a Xilinx MicroBlaze Processor.","PeriodicalId":263746,"journal":{"name":"7th International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC)","volume":"91 12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-07-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123116498","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 4

Security enhancements for FPGA-based MPSoCs: A boot-to-runtime protection flow for an embedded Linux-based system 基于fpga的mpsoc的安全性增强:嵌入式linux系统的启动到运行时保护流

7th International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC) Pub Date : 2012-07-09 DOI: 10.1109/ReCoSoC.2012.6322896

Pascal Cotret, Florian Devic, G. Gogniat, Benoît Badrignans, L. Torres

{"title":"Security enhancements for FPGA-based MPSoCs: A boot-to-runtime protection flow for an embedded Linux-based system","authors":"Pascal Cotret, Florian Devic, G. Gogniat, Benoît Badrignans, L. Torres","doi":"10.1109/ReCoSoC.2012.6322896","DOIUrl":"https://doi.org/10.1109/ReCoSoC.2012.6322896","url":null,"abstract":"Nowadays, embedded systems become more and more complex: the hardware/software codesign approach is a method to create such systems in a single chip which can be based on reconfigurable technologies such as FPGAs (Field-Programmable Gate Arrays). In such systems, data exchanges are a key point as they convey critical and confidential information and data are transmitted between several hardware modules and software layers. In case of an FPGA development life cycle, OS (Operating System) / data updates as runtime communications can be done through an insecure link: attackers can use this medium to make the system misbehave (malicious injection) or retrieve bitstream-related information (eavesdropping). Recent works propose solutions to securely boot a bitstream and the associated OS while runtime transactions are not protected. This work proposes a full boot-to-runtime protection flow of an embedded Linux kernel during boot and confidentiality/integrity protection of the external memory containing the kernel and the main application code/data. This work shows that such a solution with hardware components induces an area occupancy of 10% of a xc6vlx240t Virtex-6 FPGA while having an improved throughput for Linux booting and low-latency security for runtime protection.","PeriodicalId":263746,"journal":{"name":"7th International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC)","volume":"81 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-07-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128278240","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 7

RIVER architecture: Reconfigurable flow and fabric for parallel stream processing on FPGAs RIVER架构:fpga上并行流处理的可重构流和结构

7th International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC) Pub Date : 2012-07-09 DOI: 10.1109/ReCoSoC.2012.6322876

Dominic Hillenbrand, Christian Brugger, J. Tao, Shufan Yang, M. Balzer

{"title":"RIVER architecture: Reconfigurable flow and fabric for parallel stream processing on FPGAs","authors":"Dominic Hillenbrand, Christian Brugger, J. Tao, Shufan Yang, M. Balzer","doi":"10.1109/ReCoSoC.2012.6322876","DOIUrl":"https://doi.org/10.1109/ReCoSoC.2012.6322876","url":null,"abstract":"The RIVER architecture is a run-time configurable and programmable fabric for parallel stream processing on FPGAs. RIVER's memory architecture has been designed to support non-trivial data flows efficiently and in real-time. The individual data processing cores are called Dynamic Streaming Engines (DSE). Our cloud computing supported design flow generates hundreds of thousands different DSE cores ahead in time. At run-time users may download pre-synthesized DSE cores according to their requirements - for example area and power consumption. Furthermore, our design flow shields users from traditional HDL design flows and tedious design optimizations. However, we do not impede architectural changes but provide support for them through custom instructions and numerous design time options. Our results suggest that our architecture performs well for computational- and memory-intensive kernels such as 2-dimensional convolution. By comparison to recently published, highly specialized architectures we achieve higher clock speeds and offer additional, non-trivial features thanks to our sophisticated memory architecture.","PeriodicalId":263746,"journal":{"name":"7th International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-07-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123614194","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3

A flexible approach for compiling scilab to reconfigurable multi-core embedded systems 为可重构多核嵌入式系统编译scilab的一种灵活方法

7th International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC) Pub Date : 2012-07-09 DOI: 10.1109/ReCoSoC.2012.6322879

Timo Stripf, Oliver Oey, Thomas Bruckschlögl, Ralf König, M. Hübner, J. Becker, G. Rauwerda, K. Sunesen, N. Kavvadias, G. Dimitroulakos, K. Masselos, D. Kritharidis, N. Mitas, G. Goulas, P. Alefragis, N. Voros, Steven Derrien, D. Ménard, O. Sentieys, D. Göhringer, T. Perschke

{"title":"A flexible approach for compiling scilab to reconfigurable multi-core embedded systems","authors":"Timo Stripf, Oliver Oey, Thomas Bruckschlögl, Ralf König, M. Hübner, J. Becker, G. Rauwerda, K. Sunesen, N. Kavvadias, G. Dimitroulakos, K. Masselos, D. Kritharidis, N. Mitas, G. Goulas, P. Alefragis, N. Voros, Steven Derrien, D. Ménard, O. Sentieys, D. Göhringer, T. Perschke","doi":"10.1109/ReCoSoC.2012.6322879","DOIUrl":"https://doi.org/10.1109/ReCoSoC.2012.6322879","url":null,"abstract":"The mapping process of high performance embedded applications to today's reconfigurable multiprocessor System-on-Chip devices suffers from a complex toolchain and programming process. Thus, the efficient programming of such architectures in terms of achievable performance and power consumption is limited to experts only. Enabling them to nonexperts requires a simplified programming process that hides the complexity of the underlying hardware - introduced by software parallelism of multiple cores and the flexibility of reconfigurable architectures - to the end user. The Architecture oriented paraLlelization for high performance embedded Multi-core systems using scilAb (ALMA) European project aims to bridge these hurdles through the introduction and exploitation of a Scilab- and architecture-description-language-based toolchain which enables the efficient mapping of applications on multiprocessor platforms from high level of abstraction. This holistic solution of the toolchain allows the complexity of both the application and the architecture to be hidden, which leads to a better acceptance, reduced development costs, and shorter time-to-market.","PeriodicalId":263746,"journal":{"name":"7th International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-07-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123926297","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

Distributed control for reconfigurable FPGA systems: A high-level design approach 可重构FPGA系统的分布式控制:一种高级设计方法

7th International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC) Pub Date : 2012-07-09 DOI: 10.1109/ReCoSoC.2012.6322871

C. Trabelsi, S. Meftali, J. Dekeyser

{"title":"Distributed control for reconfigurable FPGA systems: A high-level design approach","authors":"C. Trabelsi, S. Meftali, J. Dekeyser","doi":"10.1109/ReCoSoC.2012.6322871","DOIUrl":"https://doi.org/10.1109/ReCoSoC.2012.6322871","url":null,"abstract":"Due to their exponential complexity, designing adaptation control for Reconfigurable Systems-on-Chip (RSoC) is becoming one of the most challenging tasks, resulting in longer design cycles and increased time-to-market. This paper addresses this issue and proposes a novel adaptation control design approach for FPGA-based reconfigurable systems aiming to increase design productivity. This approach combines control distribution and high-level modeling in order to decrease design complexity and enhance design reuse and scalability. Control distribution is based on allocating local control aspects (monitoring, decision and reconfiguration) to distributed controllers, while respecting global system constraints/objectives using a coordinator. High-level modeling makes use of Model-Driven Engineering and the MARTE (Modeling and Analysis of Real-Time and Embedded Systems) standard in order to move from high level models to automatic code generation, which significantly simplifies the control design. The proposed design approach is integrated in a model-driven RSoC design flow and allows to model adaptation aspects at different design levels: application, architecture, allocation and deployment, which allows to target a wide range of control requirements. In order to validate our approach, a video processing application was implemented on a reconfigurable system that contained four distributed hardware controllers.","PeriodicalId":263746,"journal":{"name":"7th International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC)","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-07-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132340880","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 5

Invited paper: On-chip monitoring for adaptive heterogeneous multicore systems 特邀论文:自适应异构多核系统的片上监控

7th International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC) Pub Date : 2012-07-09 DOI: 10.1109/ReCoSoC.2012.6322872

D. Göhringer, Mounir Chemaou, M. Hübner

引用次数: 2

Fast spiking neural network architecture for low-cost FPGA devices 低成本FPGA器件的快速尖峰神经网络架构

7th International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC) Pub Date : 2012-07-09 DOI: 10.1109/ReCoSoC.2012.6322906

T. Iakymchuk, A. R. Muñoz, J. V. Francés, M. Bataller-Mompeán

{"title":"Fast spiking neural network architecture for low-cost FPGA devices","authors":"T. Iakymchuk, A. R. Muñoz, J. V. Francés, M. Bataller-Mompeán","doi":"10.1109/ReCoSoC.2012.6322906","DOIUrl":"https://doi.org/10.1109/ReCoSoC.2012.6322906","url":null,"abstract":"Spiking Neural Networks (SNN) consist of fully interconnected computation units (neurons) based on spike processing. This type of networks resembles those found in biological systems studied by neuroscientists. This paper shows a hardware implementation for SNN. First, SNN require the inputs to be spikes, being necessary a conversion system (encoding) from digital values into spikes. For travelling spikes, each neuron interconnection is characterized by weights and delays, requiring an internal neuron processing by a Postsynaptic Potential (PSP) function and membrane potential threshold evaluation for a postsynaptic output spike generation. In order to model a real biological system by artificial SNN, the number of required neurons is very high (thousands). In this work, we propose a SNN architecture able to adapt big size networks using reduced hardware resources. While spikes are processed at 1ms time, inter spike time is used for internal calculations, a mixed serial-parallel structure allows optimized computation of all neuron output values. Results show that SNN can be accommodated using a medium-size FPGA device such as Xilinx Spartan 3 with processing speed comparable to fully parallel implementations with up to 70% resource reduction.","PeriodicalId":263746,"journal":{"name":"7th International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-07-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125202335","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 15

Systematic design and evaluation of a scalable reconfigurable multiplier scheme for HLS environments HLS环境下可扩展可重构乘法器方案的系统设计与评价

7th International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC) Pub Date : 2012-07-09 DOI: 10.1109/ReCoSoC.2012.6322890

D. Bekiaris, Efstathios Sotiriou-Xanthopoulos, G. Economakos, D. Soudris

{"title":"Systematic design and evaluation of a scalable reconfigurable multiplier scheme for HLS environments","authors":"D. Bekiaris, Efstathios Sotiriou-Xanthopoulos, G. Economakos, D. Soudris","doi":"10.1109/ReCoSoC.2012.6322890","DOIUrl":"https://doi.org/10.1109/ReCoSoC.2012.6322890","url":null,"abstract":"Modern digital design has been greatly forced to offer More-Moore integration densities and very high operation frequencies for demanding applications. In this search-for-performance race, alternative and less radical More-than-Moore solutions are emerging, like reconfigurable computing. Reconfigurable computing stands between hardware and software and promises to offer the former's performance alongside with the latter's flexibility. Research in the field deals with fine or coarse grain reconfigurable components and efficient ways to map applications onto them. In this paper, a systematic design methodology and evaluation of a coarse grain reconfigurable component targeting the ASIC domain is presented. The specific component is a morphable architecture, that works in mutually exclusive modes, offering different functionality in each mode. The novelty presented in this paper is a systematic evaluation of the scalability of the morphable component. Continuously functionally improved modes are evaluated for performance, area and power, in order to choose the best architecture for a number of widely used DSP applications. Overall, a power* performance improvement of up to 24% is reported and a power* area of up to 13% compared to conventional, non-reconfigurable component architectures.","PeriodicalId":263746,"journal":{"name":"7th International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC)","volume":"69 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-07-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124669658","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A framework for self-reconfigurable DCTs based on multiobjective optimization of the Power-Performance-Accuracy space 基于功率-性能-精度空间多目标优化的自重构dct框架

7th International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC) Pub Date : 2012-07-09 DOI: 10.1109/RECOSOC.2012.6322903

D. Llamocca, M. Pattichis, Cesar Carranza

引用次数: 5

Using genetic algorithms to map hard real-time on NoC-based systems 利用遗传算法在基于noc的系统上进行硬实时映射

7th International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC) Pub Date : 2012-07-09 DOI: 10.1109/ReCoSoC.2012.6322893

Adrian Racu, L. Indrusiak

引用次数: 42