RIVER architecture: Reconfigurable flow and fabric for parallel stream processing on FPGAs

Abstract

The RIVER architecture is a run-time configurable and programmable fabric for parallel stream processing on FPGAs. RIVER's memory architecture has been designed to support non-trivial data flows efficiently and in real-time. The individual data processing cores are called Dynamic Streaming Engines (DSE). Our cloud computing supported design flow generates hundreds of thousands different DSE cores ahead in time. At run-time users may download pre-synthesized DSE cores according to their requirements - for example area and power consumption. Furthermore, our design flow shields users from traditional HDL design flows and tedious design optimizations. However, we do not impede architectural changes but provide support for them through custom instructions and numerous design time options. Our results suggest that our architecture performs well for computational- and memory-intensive kernels such as 2-dimensional convolution. By comparison to recently published, highly specialized architectures we achieve higher clock speeds and offer additional, non-trivial features thanks to our sophisticated memory architecture.