7th International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC)最新文献_第2页

Dynamically reconfigurable flux limiter functions in MUSCL scheme MUSCL方案中动态可重构的通量限制器函数

7th International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC) Pub Date : 2012-07-09 DOI: 10.1109/ReCoSoC.2012.6322878

M. S. A. Talip, Takayuki Akamine, Yasunori Osana, N. Fujita, H. Amano

{"title":"Dynamically reconfigurable flux limiter functions in MUSCL scheme","authors":"M. S. A. Talip, Takayuki Akamine, Yasunori Osana, N. Fujita, H. Amano","doi":"10.1109/ReCoSoC.2012.6322878","DOIUrl":"https://doi.org/10.1109/ReCoSoC.2012.6322878","url":null,"abstract":"In aerospace application, computational fluid dynamics (CFD) is recognized as a cost effective design tool. UPACS, a package for CFD is convenient for users, which has various solvers to support large scale of complexity. The problem is its computation speed which is hard to be enhanced by using clusters due to its complex memory access patterns. As an economical solution, accelerators using FPGAs are hopeful candidates. However, the total scale of UPACS is too large to be implemented on small numbers of FPGAs. For cost efficient implementation, partial reconfiguration which can dynamically reconfigure only required functions is proposed in this paper. MUSCL scheme, a main function used frequently in UPACS is selected as a target. Partial reconfiguration is applied to the flux limiter functions in MUSCL. Two reconfigurable partitions are created for Turbulence MUSCL and Convection MUSCL. All limiter functions are developed independently and synthesized separately from the top MUSCL module. Required limiter functions for both MUSCLs are loaded dynamically without interfering each other operation. This implementation has successfully reduced the resource utilization by 60%. Total power consumption is also reduced by 29%. Configuration speed is improved by 15-times faster as compared to fully reconfiguration method. All implemented functions achieved at least 17 times speed-up compared with the software implementation.","PeriodicalId":263746,"journal":{"name":"7th International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-07-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128094705","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

MPSoCDK: A framework for prototyping and validating MPSoC projects on FPGAs MPSoCDK:用于在fpga上原型化和验证MPSoC项目的框架

7th International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC) Pub Date : 2012-07-09 DOI: 10.1109/ReCoSoC.2012.6322891

R. Langendonck, A. K. Lusala, J. Legat

引用次数: 9

Hardware acceleration of combined cipher and forward error correction for low-power wireless applications 低功耗无线应用中组合密码和前向纠错的硬件加速

7th International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC) Pub Date : 2012-07-09 DOI: 10.1109/ReCoSoC.2012.6322886

F. Philipp, C. Klytta, M. Glesner, Élvio Dutra

引用次数: 2

Exploiting FPGA-aware merging of custom instructions for runtime reconfiguration 利用fpga感知的自定义指令合并来进行运行时重新配置

7th International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC) Pub Date : 2012-07-09 DOI: 10.1145/2655240

S. Lam, T. Srikanthan, C. Clarke

引用次数: 4

Smart technologies for effective reconfiguration: The FASTER approach 有效重新配置的智能技术:更快的方法

7th International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC) Pub Date : 2012-07-09 DOI: 10.1109/RECOSOC.2012.6322881

M. Santambrogio, D. Pnevmatikatos, Kyprianos Papademetriou, C. Pilato, G. Gaydadjiev, D. Stroobandt, Tom Davidson, Tobias Becker, T. Todman, W. Luk, A. Bonetto, Andrea Cazzaniga, Gianluca Durelli, D. Sciuto

{"title":"Smart technologies for effective reconfiguration: The FASTER approach","authors":"M. Santambrogio, D. Pnevmatikatos, Kyprianos Papademetriou, C. Pilato, G. Gaydadjiev, D. Stroobandt, Tom Davidson, Tobias Becker, T. Todman, W. Luk, A. Bonetto, Andrea Cazzaniga, Gianluca Durelli, D. Sciuto","doi":"10.1109/RECOSOC.2012.6322881","DOIUrl":"https://doi.org/10.1109/RECOSOC.2012.6322881","url":null,"abstract":"Current and future computing systems increasingly require that their functionality stays flexible after the system is operational, in order to cope with changing user requirements and improvements in system features, i.e. changing protocols and data-coding standards, evolving demands for support of different user applications, and newly emerging applications in communication, computing and consumer electronics. Therefore, extending the functionality and the lifetime of products requires the addition of new functionality to track and satisfy the customers needs and market and technology trends. Many contemporary products along with the software part incorporate hardware accelerators for reasons of performance and power efficiency. While adaptivity of software is straightforward, adaptation of the hardware to changing requirements constitutes a challenging problem requiring delicate solutions. The FASTER (Facilitating Analysis and Synthesis Technologies for Effective Reconfiguration) project aims at introducing a complete methodology to allow designers to easily implement a system specification on a platform which includes a general purpose processor combined with multiple accelerators running on an FPGA, taking as input a high-level description and fully exploiting, both at design time and at run time, the capabilities of partial dynamic reconfiguration. The goal is that for selected application domains, the FASTER toolchain will be able to reduce the design and verification time of complex reconfigurable systems providing additional novel verification features that are not available in existing tool flows.","PeriodicalId":263746,"journal":{"name":"7th International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC)","volume":"55 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-07-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123592784","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 6

Hardware implementation of GMDH-type artificial neural networks and its use to predict approximate three-dimensional structures of proteins gmdh型人工神经网络的硬件实现及其在预测蛋白质近似三维结构中的应用

7th International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC) Pub Date : 2012-07-09 DOI: 10.1109/ReCoSoC.2012.6322907

A. Braga, J. Arias-Garcia, C. Llanos, M. Dorn, A. Foltran, L. Coelho

{"title":"Hardware implementation of GMDH-type artificial neural networks and its use to predict approximate three-dimensional structures of proteins","authors":"A. Braga, J. Arias-Garcia, C. Llanos, M. Dorn, A. Foltran, L. Coelho","doi":"10.1109/ReCoSoC.2012.6322907","DOIUrl":"https://doi.org/10.1109/ReCoSoC.2012.6322907","url":null,"abstract":"Implementation of artificial neural networks in software on general purpose computer platforms are brought to an advanced level both in terms of performance and accuracy. Nonetheless, neural networks are not so easily applied in embedded systems, specially when the fully retraining of the network is required. This paper shows the results of the implementation of artificial neural networks based on the Group Method of Data Handling (GMDH) in reconfigurable hardware, both in the steps of training and running. A hardware architecture has been developed to be applied as a co-processing unit and an example application has been used to test its functionality. The application has been developed for the prediction of approximate 3-D structures of proteins. A set of experiments have been performed on a PC using the FPGA as a co-processor accessed through sockets over the TCP/IP protocol. The design flow employed demonstrated that it is possible to implement the network in hardware to be easily applied as an accelerator in embedded systems. The experiments show that the proposed implementation is effective in finding good quality solutions for the example problem. This work represents the early results of the novel technique of applying the GMDH algorithms in hardware for solving the problem of protein structures prediction.","PeriodicalId":263746,"journal":{"name":"7th International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC)","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-07-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121502523","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 4

Partially reconfigurable TVWS transceiver for use in UK and US markets 部分可重构的TVWS收发器用于英国和美国市场

7th International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC) Pub Date : 2012-07-09 DOI: 10.1109/ReCoSoC.2012.6322904

R. Elliot, M. A. Enderwitz, Ke He, F. Darbari, L. Crockett, Stephan Weiss, R. Stewart

引用次数: 4

A heterogeneous modules interconnection architecture for FPGA-based partial dynamic reconfiguration 基于fpga的局部动态重构异构模块互连体系结构

7th International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC) Pub Date : 2012-07-09 DOI: 10.1109/ReCoSoC.2012.6322887

Miao He, Yanzhe Cui, M. Mahoor, R. Voyles

引用次数: 8

Automatic run-time manager generation for reconfigurable MPSoC architectures 自动运行时管理器生成可重构的MPSoC架构

7th International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC) Pub Date : 2012-07-09 DOI: 10.1109/ReCoSoC.2012.6322883

Gianluca Durelli, C. Pilato, Andrea Cazzaniga, D. Sciuto, M. Santambrogio

{"title":"Automatic run-time manager generation for reconfigurable MPSoC architectures","authors":"Gianluca Durelli, C. Pilato, Andrea Cazzaniga, D. Sciuto, M. Santambrogio","doi":"10.1109/ReCoSoC.2012.6322883","DOIUrl":"https://doi.org/10.1109/ReCoSoC.2012.6322883","url":null,"abstract":"During the last few years, new technologies have made possible to fit a larger number of components on a single die, allowing to realize more complex and heterogeneous systems, generally called Multiprocessor Systems-on-Chip (MPSoC). Additionally, the introduction of partial reconfiguration in these systems has increased both their flexibility and performance. This feature allows the designer to switch the context of a specific circuit region without any interruption in the other components, but it has also increased the level of expertise needed for their design. In this paper we introduce a Run Time Manager (RTM) able to map multiple applications on the underlying architecture and execute them concurrently. In order to ensure the RTM portability on different designs, it has been structured so that it is independent from the architecture description. It is illustrated how (1) this RTM can be automatically generated starting from the source code of the input applications, (2) its modular implementation combined with the use of partial reconfiguration allows the user to explore different policies. Finally several tests have been performed to analyse the overhead introduced by such implementation and to demonstrate that the proposed RTM can be effectively used in real case studies.","PeriodicalId":263746,"journal":{"name":"7th International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-07-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115025727","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 9

MADES FP7 EU project: Effective high level SysML/MARTE methodology for real-time and embedded avionics systems MADES FP7欧盟项目:用于实时和嵌入式航空电子系统的有效高级SysML/MARTE方法

7th International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC) Pub Date : 2012-07-09 DOI: 10.1109/ReCoSoC.2012.6322882

I. Quadri, E. Brosse, Ian Gray, N. Matragkas, L. Indrusiak, M. Rossi, A. Bagnato, A. Sadovykh

引用次数: 30