2018 International Symposium on Semiconductor Manufacturing (ISSM)最新文献

{"title":"Advanced Process Control Using Virtual Metrology to Cope with Etcher Condition Change","authors":"Shota Umeda, Keita Nogi, Daisuke Shiraishi, A. Kagoshima","doi":"10.1109/issm.2018.8651162","DOIUrl":"https://doi.org/10.1109/issm.2018.8651162","url":null,"abstract":"In a semiconductor plasma etcher, an advanced process control (APC) system using virtual metrology (VM) is required to achieve further device miniaturization. Although a highly accurate VM model is necessary to realize the system, the prediction accuracy can be worse when correlations between the critical dimension (CD) and equipment data change because of changes in etcher conditions. To solve the problem, we propose a multiple VM model selection APC system. This paper shows that the proposed system contributes to improving prediction accuracy even though the correlation change occurs by simulation based on the actual etcher experimental data.","PeriodicalId":262428,"journal":{"name":"2018 International Symposium on Semiconductor Manufacturing (ISSM)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132566331","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"ISSM 2018 TOC","authors":"","doi":"10.1109/issm.2018.8651165","DOIUrl":"https://doi.org/10.1109/issm.2018.8651165","url":null,"abstract":"","PeriodicalId":262428,"journal":{"name":"2018 International Symposium on Semiconductor Manufacturing (ISSM)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126273187","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Inline scratch defect detection at post CMP step in FinFET device processing","authors":"M. I. Hossain, Sean Le, Dale R Sheu","doi":"10.1109/ISSM.2018.8651184","DOIUrl":"https://doi.org/10.1109/ISSM.2018.8651184","url":null,"abstract":"FinFETs have a complex structure which poses challenges for high volume semiconductor device processing. It is critical to mitigate these challenges for optimum device performance. CMP (Chemical Mechanical Polishing) is an integral part of semiconductor device processing. An accurate polishing becomes more and more difficult as we move toward smaller technology nodes. On one hand it is crucial to polish different layers at an optimized rate and amount; while on the other hand, this also enhances the possibility of scratching the wafer surface and the structures on top. As part of defect metrology it is of utmost importance to catch these defects inline and take timely actions to minimize the adverse effect on process yield. In certain layers the detection of these scratches are not very straight forward. Hence in this work as part of metrology inspection improvement we report the detection of this type of scratches. Here, we describe our experiment to catch scratch defects using lower wavelength inspection tools. Effective inline detection of these defects improves the device performance and accounts for yield concerns.","PeriodicalId":262428,"journal":{"name":"2018 International Symposium on Semiconductor Manufacturing (ISSM)","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125259472","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Predictive process control for change in chemical dry etching equipment condition","authors":"Miyuki Maruta, Y. Oomuro, Kazutaka Nagashima","doi":"10.1109/ISSM.2018.8651130","DOIUrl":"https://doi.org/10.1109/ISSM.2018.8651130","url":null,"abstract":"In semiconductor production, a compound abnormal factor is undetectable in independent QC (Quality Control) and equipment log management. It is a problem to influence the low yield of semiconductor manufacturing. The predictive model was created by the relation of processing form and some parameters. The motif is CDE (Chemical Dry Etching) equipment. Equipment control using predictive model was considered. Management system was established by monitoring the difference of predicted value and actual value.","PeriodicalId":262428,"journal":{"name":"2018 International Symposium on Semiconductor Manufacturing (ISSM)","volume":"198 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125730536","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Resist coating and developing process technology toward EUV manufacturing sub 7nm node","authors":"Y. Kamei, T. Shiozawa, S. Kawakami, H. Shite, Hiroshi Ichinomiya, Yusaku Hashimoto, M. Enomoto, K. Nafus, Akihiko Sonoda, M. Demand, P. Foubert","doi":"10.1117/12.2297203","DOIUrl":"https://doi.org/10.1117/12.2297203","url":null,"abstract":"Extreme ultraviolet lithography (EUVL) is getting closer to practical use for mass production every year. For applying EUV lithography to manufacturing, productivity improvement is a critical challenge. Throughput and yield are important factors for productivity. EUV source power is steadily advancing year by year, bringing improvements in throughput. Furthermore, yield improvement is necessary for productivity enhancement. In order to improve the yield in EUV lithography processing, further improvement of defectivity and critical dimension (CD) uniformity is required. Reduction of residue and in-film particle defects is very crucial work to enhance the productivity. For residue defects, it is found that the residue defects detected after development inspection (ADI) are perfectly transferred to after etching inspection (AEI), meaning that high defectivity of residue deteriorates yield directly. Furthermore, in-film particle defect counts increase from ADI to AEI because particles included in spin-on-carbon (SOC) and spin-on-glass (SOG) as well as that in resist film are the sources of defects in AEI, while particles mainly included in resist film can be observed in ADI. Figure 1 shows the normalized defectivity comparison between conventional rinse and filtration used and optimizing rinse used and improving filtration efficiency in ADI and AEI. ADI defectivity in which optimized rinse is applied and improving filtration efficiency achieved 0.04, while that in which conventional rinse and filtration are used defined 1.00, meaning the 96 % of improvement. In addition, AEI defectivity by using optimized rinse and improving of filtration efficiency shows 86 % of reduction as compared with that using conventional rinse and filtration. These results reveal that our novel actions for rinse and material supply show excellent performance for defect reduction. For the other aspect of yield improvement, CD uniformity control is one of the crucial factors. CD variations are comprised of several components such as wafer to wafer CD uniformity, field to field CD uniformity. To achieve CD uniformity target for manufacturing, we have optimized developing process with the latest technology. Then, 15 % of field to field CD uniformity improvement and significant improvement of wafer to wafer CD uniformity are achieved.","PeriodicalId":262428,"journal":{"name":"2018 International Symposium on Semiconductor Manufacturing (ISSM)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-03-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120962329","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"An Accurate Method for Determining Pattern Collapse Occurrence for Nano-Structures","authors":"H. Marumoto, M. Nakamori, H. Kawano","doi":"10.1109/ISSM.2018.8651156","DOIUrl":"https://doi.org/10.1109/ISSM.2018.8651156","url":null,"abstract":"Pattern collapse of nano-structures during the wet cleaning process is one of the main problems which leads to poor device yield. In general, aspect ratio (AR) is often used as the indicator for determining the likelihood of pattern collapse occurrence, because high aspect ratio structures tend to collapse more easily. However, pattern collapse is also influenced by flexural rigidity of the structures, material, and shape. Therefore, AR lacks versatility in comparing different structures and material. We propose “$gamma_{PC}$” as the substitute parameter for aspect ratio. In this paper, we indicate with experimental data that $gamma_{PC}$ is more accurate than aspect ratio, and can be used to quantitatively determine the pattern collapse prevention performance of dry technologies.}","PeriodicalId":262428,"journal":{"name":"2018 International Symposium on Semiconductor Manufacturing (ISSM)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-08-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125729854","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}