2019 IEEE 28th Asian Test Symposium (ATS)最新文献_第3页

Design of a Sextuple Cross-Coupled SRAM Cell with Optimized Access Operations for Highly Reliable Terrestrial Applications 高可靠地面应用六重交叉耦合SRAM单元的优化访问操作设计

2019 IEEE 28th Asian Test Symposium (ATS) Pub Date : 2019-12-01 DOI: 10.1109/ATS47505.2019.00006

Aibin Yan, Zhen Wu, Jun Zhou, Yuanjie Hu, Yan Chen, Zuobin Ying, X. Wen, P. Girard

引用次数: 7

Title Page i 第1页

2019 IEEE 28th Asian Test Symposium (ATS) Pub Date : 2019-12-01 DOI: 10.1109/ats47505.2019.00001

引用次数: 0

Machine Learning Assisted Accurate Estimation of Usage Duration and Manufacturer for Recycled and Counterfeit Flash Memory Detection 机器学习辅助准确估计使用时间和制造商的回收和假冒闪存检测

2019 IEEE 28th Asian Test Symposium (ATS) Pub Date : 2019-12-01 DOI: 10.1109/ATS47505.2019.000-1

Saranyu Chattopadhyay, P. Kumari, B. Ray, R. Chakraborty

{"title":"Machine Learning Assisted Accurate Estimation of Usage Duration and Manufacturer for Recycled and Counterfeit Flash Memory Detection","authors":"Saranyu Chattopadhyay, P. Kumari, B. Ray, R. Chakraborty","doi":"10.1109/ATS47505.2019.000-1","DOIUrl":"https://doi.org/10.1109/ATS47505.2019.000-1","url":null,"abstract":"With the large-scale adaptation of a \"horizontal\" business model, modern semiconductor supply chain is plagued by recycled and counterfeit ICs, including flash memory chips. Since flash memory modules have an inherently finite lifespan, detection of recycled flash memory chips before their deployment in safety-critical systems is important to prevent disastrous consequences. The state-of-art detection methods can detect flash memory modules between 0.05% to 3.00% of their lifespan as minimum usage duration, depending on the details of the flash memory chip. In this paper, we propose a versatile machine learning assisted detection methodology to improve the minimum usage duration accuracy between 0.05% to 0.96% of their lifespan, and also to accurately associate a flash memory IC with its manufacturer. Through detailed experimentation and comparison of detection results obtained using three popular supervised machine learning techniques (Support Vector Machines, Logistic Regression and Artificial Neural Networks), we demonstrate that usage of features composed of multiple characteristics of a given chip, rather than just a single property of a chip (as used in previous works), improves detection accuracy.","PeriodicalId":258824,"journal":{"name":"2019 IEEE 28th Asian Test Symposium (ATS)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128829862","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 5

TEA: A Test Generation Algorithm for Designs with Timing Exceptions TEA:具有时序异常设计的测试生成算法

2019 IEEE 28th Asian Test Symposium (ATS) Pub Date : 2019-12-01 DOI: 10.1109/ATS47505.2019.000-6

Naixing Wang, Chen Wang, Kun-Han Tsai, Wu-Tung Cheng, X. Lin, M. Kassab, I. Pomeranz

{"title":"TEA: A Test Generation Algorithm for Designs with Timing Exceptions","authors":"Naixing Wang, Chen Wang, Kun-Han Tsai, Wu-Tung Cheng, X. Lin, M. Kassab, I. Pomeranz","doi":"10.1109/ATS47505.2019.000-6","DOIUrl":"https://doi.org/10.1109/ATS47505.2019.000-6","url":null,"abstract":"Timing exceptions are commonly used to indicate that the timing of certain paths have been relaxed so as to enable the design to meet timing closure. Generating scan-based test patterns without considering timing exceptions can lead to invalid test responses, resulting in unpredictable test quality impact. The existing simulation-based solution masks out unreliable signals after a test pattern is generated. If the signals required for detecting the target fault are unreliable and masked out, the generated test pattern fails to detect the target fault, and it is discarded. To achieve an acceptable test coverage, several iterations of test generation with a randomized decision-making process are typically required where different tests are generated for target faults. In this paper, an innovative deterministic ATPG algorithm called TEA (Timing Exception ATPG) is proposed to prevent the generated test patterns from being impacted by timing exceptions. The deterministic algorithm is compatible with the existing simulation-based approach. In this simulation environment, TEA is complete such that for a target fault, the test pattern generated is guaranteed to detect it. If a test pattern cannot be generated using TEA, the target fault is untestable given the timing exception paths in the design and the existing simulation environment. Compared to the existing simulation-based approach, using TEA can generate a more effective test set, improving test coverage, test pattern count, and the total ATPG run time significantly.","PeriodicalId":258824,"journal":{"name":"2019 IEEE 28th Asian Test Symposium (ATS)","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124683866","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 4

ATS 2019 Industry Forum Invited Talks ATS 2019行业论坛特邀演讲

2019 IEEE 28th Asian Test Symposium (ATS) Pub Date : 2019-12-01 DOI: 10.1109/ats47505.2019.00-11

引用次数: 0

ATS 2019 Student Committee ATS 2019学生委员会

2019 IEEE 28th Asian Test Symposium (ATS) Pub Date : 2019-12-01 DOI: 10.1109/ats47505.2019.00-16

引用次数: 0

ATS 2019 Invited Talks [5 abstracts] ATS 2019特邀演讲[5个摘要]

2019 IEEE 28th Asian Test Symposium (ATS) Pub Date : 2019-12-01 DOI: 10.1109/ats47505.2019.00-13

引用次数: 0

About the 2019 IEEE 28th Asian Test Symposium 关于2019 IEEE第28届亚洲测试研讨会

2019 IEEE 28th Asian Test Symposium (ATS) Pub Date : 2019-12-01 DOI: 10.1109/ats47505.2019.00005

引用次数: 0

ATS 2019 Tutorials

2019 IEEE 28th Asian Test Symposium (ATS) Pub Date : 2019-12-01 DOI: 10.1109/ats47505.2019.00-12

引用次数: 0

ATS 2019 Steering Committee ATS 2019指导委员会

2019 IEEE 28th Asian Test Symposium (ATS) Pub Date : 2019-12-01 DOI: 10.1109/ats47505.2019.00009

Michiko Inoue, Huawei Li, B. Bhattacharya, Tomoo Inoue, Kuen-Jong Lee

引用次数: 0