2019 IEEE 28th Asian Test Symposium (ATS)最新文献

Fault Coverage of a Test Set on Structure-Preserving Siblings of a Circuit-Under-Test 被测电路保持结构兄弟上测试集的故障覆盖率

2019 IEEE 28th Asian Test Symposium (ATS) Pub Date : 2019-12-01 DOI: 10.1109/ATS47505.2019.000-5

Manobendra Nath Mondal, A. B. Chowdhury, Manjari Pradhan, S. Sur-Kolay, B. Bhattacharya

{"title":"Fault Coverage of a Test Set on Structure-Preserving Siblings of a Circuit-Under-Test","authors":"Manobendra Nath Mondal, A. B. Chowdhury, Manjari Pradhan, S. Sur-Kolay, B. Bhattacharya","doi":"10.1109/ATS47505.2019.000-5","DOIUrl":"https://doi.org/10.1109/ATS47505.2019.000-5","url":null,"abstract":"Most of the Automatic Test Pattern Generation (ATPG) algorithms for digital circuits rely heavily on netlist description that comprises both network interconnect structure among logic gates and the functionality of each gate. The performance of an ATPG tool on a circuit-under-test (CUT) C is determined by the size of the test set T and its fault coverage (FC). Despite extensive research in the field of testing, the following question remains unanswered: Is the structure or the functionality of C dominant in determining FC of a test-set T for C? In this paper, we present empirical evidence in favour of the dominance of structure on FC by randomly selecting a logic gate from a synthesized netlist for C, and replacing it by a different type of gate. Our experiments provide an un-intuitive result that F C of a test-set T for C under the single stuck-at fault model remains nearly the same on other sibling circuits that have identical structure as of C but with different gate functionality, provided these have similar extent of fault redundancy. This observation supports the view that feeding structural information alone may suffice to train machine-learning models that are currently being used to expedite different problems of digital circuit testing and diagnosis.","PeriodicalId":258824,"journal":{"name":"2019 IEEE 28th Asian Test Symposium (ATS)","volume":"83 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122627210","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

Machine-Learning-Based Multiple Abstraction-Level Detection of Hardware Trojan Inserted at Register-Transfer Level 基于机器学习的多抽象层检测在寄存器传输层插入的硬件木马

2019 IEEE 28th Asian Test Symposium (ATS) Pub Date : 2019-12-01 DOI: 10.1109/ATS47505.2019.00018

Hau Sim Choo, C. Y. Ooi, M. Inoue, N. Ismail, M. Moghbel, Sreedharan Baskara Dass, Chee Hoo Kok, F. Hussin

引用次数: 4

Net Classification Based on Testability and Netlist Structural Features for Hardware Trojan Detection 基于可测试性和网表结构特征的网络分类在硬件木马检测中的应用

2019 IEEE 28th Asian Test Symposium (ATS) Pub Date : 2019-12-01 DOI: 10.1109/ATS47505.2019.00020

Chee Hoo Kok, C. Y. Ooi, M. Inoue, M. Moghbel, Sreedharan Baskara Dass, Hau Sim Choo, N. Ismail, F. Hussin

{"title":"Net Classification Based on Testability and Netlist Structural Features for Hardware Trojan Detection","authors":"Chee Hoo Kok, C. Y. Ooi, M. Inoue, M. Moghbel, Sreedharan Baskara Dass, Hau Sim Choo, N. Ismail, F. Hussin","doi":"10.1109/ATS47505.2019.00020","DOIUrl":"https://doi.org/10.1109/ATS47505.2019.00020","url":null,"abstract":"As integrated chip (IC) is one of the most essential components for communication devices, enhancing the integrity of hardware security is essential to prevent any security breach. Implantation of Hardware Trojan (HT) into the IC is one of the most threatening hardware security risks since most of the IC design and fabrication phases are outsourced to third-party foundries. Gate-level netlist inspection is utterly important as HT could be easily hidden among the primitives of the circuit which makes the detection challenging. Previously, HT detection methods for gate-level netlist were mainly based on either net testability or net's structural features. In this paper, we proposed to consolidate these two types of features into a single feature vector to train supervised machine learning classifiers. We also analyzed the performance of the classifiers based on different combinations of features using Minimum Redundancy and Maximum Relevance (mRMR) technique. Using the best feature combination, we achieved a 99.85% True Positive Rate (TPR), 99.95% True Negative Rate (TNR) and 99.90% accuracy (ACC). The results were validated using 10-fold cross-validation.","PeriodicalId":258824,"journal":{"name":"2019 IEEE 28th Asian Test Symposium (ATS)","volume":"74 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130426348","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 9

Recruiting Fault Tolerance Techniques for Microprocessor Security 微处理器安全中的容错技术

2019 IEEE 28th Asian Test Symposium (ATS) Pub Date : 2019-12-01 DOI: 10.1109/ATS47505.2019.00015

Vinay B. Y. Kumar, S. Deb, Rupesh Kumar, Mustafa Khairallah, A. Chattopadhyay, A. Mendelson

{"title":"Recruiting Fault Tolerance Techniques for Microprocessor Security","authors":"Vinay B. Y. Kumar, S. Deb, Rupesh Kumar, Mustafa Khairallah, A. Chattopadhyay, A. Mendelson","doi":"10.1109/ATS47505.2019.00015","DOIUrl":"https://doi.org/10.1109/ATS47505.2019.00015","url":null,"abstract":"The growing threat of various attacks on modern microprocessors and systems calls for major design overhauls ranging from plugging micro-architectural side channels such as due to speculative execution to implementing cryptographic accelerators for side-channel and fault attack resistance. In this paper, we suggest to focus on the similarities and the differences between fault tolerance techniques and countermeasures against attacks on security sensitive systems. Modern digital circuits and systems use a diverse set of techniques to ensure operational correctness in the presence of faults. From a security perspective, the goal is to ensure a set of stated security properties hold in the presence of 'security faults' (extending the notion of conventional faults to include injected faults as well as vulnerabilities such as passive side-channels). A point of note here is that under some security faults, the operational correctness may not be compromised. This paper advocates the re-purposing of some of the known fault tolerance techniques, and show how those can be useful for enhancing security in the presence of active side-channel attacks. As a simple illustration of these ideas, we present an experimental case study in fortifying a cryptographic sub-component of a RISC-V based secure system-on-chip, against a formidable fault attack called SIFA.","PeriodicalId":258824,"journal":{"name":"2019 IEEE 28th Asian Test Symposium (ATS)","volume":"50 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114567161","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

A Structured Approach for Rapid Identification of Fault-Sensitive Nets in Analog Circuits 模拟电路中故障敏感网络快速识别的结构化方法

2019 IEEE 28th Asian Test Symposium (ATS) Pub Date : 2019-12-01 DOI: 10.1109/ATS47505.2019.00025

Sayandeep Sanyal, A. Patra, P. Dasgupta, M. Bhattacharya

引用次数: 7

Detailed Fault Model for Physical Quantum Circuits 物理量子电路的详细故障模型

2019 IEEE 28th Asian Test Symposium (ATS) Pub Date : 2019-12-01 DOI: 10.1109/ATS47505.2019.00028

Arighna Deb, D. K. Das

引用次数: 2

Message from the ATS 2019 Program Co-Chairs ATS 2019项目联合主席致辞

2019 IEEE 28th Asian Test Symposium (ATS) Pub Date : 2019-12-01 DOI: 10.1109/ats47505.2019.00-22

引用次数: 0

GramsDet: Hardware Trojan Detection Based on Recurrent Neural Network 基于递归神经网络的硬件木马检测

2019 IEEE 28th Asian Test Symposium (ATS) Pub Date : 2019-12-01 DOI: 10.1109/ATS47505.2019.00021

Renjie Lu, Haihua Shen, Yu Su, Huawei Li, Xiaowei Li

引用次数: 9

Novel Radiation Hardened Latch Design with Cost-Effectiveness for Safety-Critical Terrestrial Applications 具有成本效益的新型辐射硬化锁存设计，用于安全关键的地面应用

2019 IEEE 28th Asian Test Symposium (ATS) Pub Date : 2019-12-01 DOI: 10.1109/ATS47505.2019.000-2

Aibin Yan, Zhen Wu, Lu Lu, Zhili Chen, Jie Song, Zuobin Ying, P. Girard, X. Wen

引用次数: 1

Title Page iii 第三页标题

2019 IEEE 28th Asian Test Symposium (ATS) Pub Date : 2019-12-01 DOI: 10.1109/ats47505.2019.00002

引用次数: 0