ISLPED '05. Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005.最新文献_第5页

Systematic power reduction and performance analysis of mismatch limited ADC designs 系统的功率降低和失配限制ADC设计的性能分析

ISLPED '05. Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005. Pub Date : 2005-08-08 DOI: 10.1145/1077603.1077622

P. Scholtens, D. Smola, M. Vertregt

引用次数: 13

Energy-efficient and high-performance instruction fetch using a block-aware ISA 使用块感知ISA的节能和高性能指令获取

ISLPED '05. Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005. Pub Date : 2005-08-08 DOI: 10.1145/1077603.1077614

Ahmad Zmily, C. Kozyrakis

引用次数: 8

Peak temperature control and leakage reduction during binding in high level synthesis 高水平合成中结合过程中的峰值温度控制和泄漏减少

ISLPED '05. Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005. Pub Date : 2005-08-08 DOI: 10.1145/1077603.1077663

R. Mukherjee, S. Memik, G. Memik

{"title":"Peak temperature control and leakage reduction during binding in high level synthesis","authors":"R. Mukherjee, S. Memik, G. Memik","doi":"10.1145/1077603.1077663","DOIUrl":"https://doi.org/10.1145/1077603.1077663","url":null,"abstract":"Temperature is becoming a first rate design criterion in ASICs due to its negative impact on leakage power, reliability, performance, and packaging cost. Incorporating awareness of such lower level physical phenomenon in high level synthesis algorithms help to achieve better designs. In this work, we developed a temperature aware binding algorithm. Switching power of a module correlates with its operating temperature. The goal of our binding algorithm is to distribute the activity evenly across functional units. This approach avoids steep temperature differences between modules on a chip, hence, the occurrence of hot spots. Starting with a switching optimal binding solution, our algorithm iteratively minimizes the maximum temperature reached by the hottest functional unit. Our algorithm does not change the number of resources used in the original binding. We have used HotSpot, a temperature modeling tool, to simulate temperature of a number ASIC designs. Our binding algorithm reduces temperature reached by the hottest resource by 12.21/spl deg/C on average. Reducing the peak temperature has a positive impact on leakage as well. Our binding technique improves leakage power by 11.89%, and overall power by 3.32% on average at 130nm technology node compared to a switching optimal binding.","PeriodicalId":256018,"journal":{"name":"ISLPED '05. Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005.","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-08-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134074791","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 21

Instruction packing: reducing power and delay of the dynamic scheduling logic 指令封装:减少动态调度逻辑的功耗和延迟

ISLPED '05. Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005. Pub Date : 2005-08-08 DOI: 10.1145/1077603.1077613

J. Sharkey, D. Ponomarev, K. Ghose, O. Ergin

引用次数: 28

Dataflow analysis for energy-efficient scratch-pad memory management 节能刮刮板内存管理的数据流分析

ISLPED '05. Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005. Pub Date : 2005-08-08 DOI: 10.1145/1077603.1077682

Guangyu Chen, M. Kandemir

引用次数: 4

Improving energy efficiency by making DRAM less randomly accessed 通过减少随机存取DRAM来提高能源效率

ISLPED '05. Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005. Pub Date : 2005-08-08 DOI: 10.1145/1077603.1077696

Hai Huang, K. Shin, C. Lefurgy, T. Keller

引用次数: 105

A simple mechanism to adapt leakage-control policies to temperature 一个简单的机制，使泄漏控制策略适应温度

ISLPED '05. Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005. Pub Date : 2005-08-08 DOI: 10.1145/1077603.1077617

S. Kaxiras, Polychronis Xekalakis, G. Keramidas

{"title":"A simple mechanism to adapt leakage-control policies to temperature","authors":"S. Kaxiras, Polychronis Xekalakis, G. Keramidas","doi":"10.1145/1077603.1077617","DOIUrl":"https://doi.org/10.1145/1077603.1077617","url":null,"abstract":"Leakage power reduction in cache memories continues to be a critical area of research because of the promise of a significant pay-off. Various techniques have been developed so far that can be broadly categorized into state-preserving (e.g., drowsy caches) and nonstate preserving (e.g., cache decay). Decay saves more leakage but also incurs dynamic power overhead in the form of induced misses. Previous work has shown that depending on the leakage vs. dynamic power trade-off, one or the other technique can be better. Several factors such as cache architecture, technology parameters and temperature, affect this trade-off. Our work proposes the first mechanism - to the best of our knowledge - that takes into account temperature in adjusting the leakage control policy at run time. At very low temperatures, leakage is relatively weak so the need to tightly control it is not as important as the need to minimize extra dynamic power (e.g., decay-induced misses) or performance loss. We use a hybrid decay+drowsy policy where the main benefit comes from decaying cache lines while the drowsy mode is used to save leakage in long decay intervals. To adapt the decay mode to temperature, we propose a simple triggering mechanism that is based on the principles of decaying 4T thermal sensors and, as such, tied to temperature. The hotter the cache is, the faster cache lines are decayed since it is beneficial to do so with very high leakage currents. Conversely, when the cache temperature is low, our mechanism defers putting cache lines in decay mode to avoid dynamic power overhead but still saves a significant amount of leakage using the drowsy mode. Our study shows that across a wide range of temperatures, the simple adaptability of our proposal yields consistently better results than either the decay mode, or drowsy mode alone, improving over the best by as much as 33%.","PeriodicalId":256018,"journal":{"name":"ISLPED '05. Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005.","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-08-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115408536","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 16

Runtime identification of microprocessor energy saving opportunities 运行时识别微处理器的节能机会

ISLPED '05. Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005. Pub Date : 2005-08-08 DOI: 10.1145/1077603.1077668

W. Bircher, M. Valluri, J. Law, L. John

引用次数: 112

Replacing global wires with an on-chip network: a power analysis 用片上网络代替全球电线:功率分析

ISLPED '05. Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005. Pub Date : 2005-08-08 DOI: 10.1145/1077603.1077692

Seongmoo Heo, K. Asanović

引用次数: 68

Modeling and analysis of total leakage currents in nanoscale double gate devices and circuits 纳米双栅器件和电路中总泄漏电流的建模与分析

ISLPED '05. Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005. Pub Date : 2005-08-08 DOI: 10.1145/1077603.1077608

S. Mukhopadhyay, Keunwoo Kim, C. Chuang, K. Roy

引用次数: 9