ISLPED '05. Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005.最新文献_第4页

Power reduction by varying sampling rate 通过改变采样率来降低功率

ISLPED '05. Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005. Pub Date : 2005-08-08 DOI: 10.1145/1077603.1077658

W. Dieter, S. Datta, Wong Key Kai

{"title":"Power reduction by varying sampling rate","authors":"W. Dieter, S. Datta, Wong Key Kai","doi":"10.1145/1077603.1077658","DOIUrl":"https://doi.org/10.1145/1077603.1077658","url":null,"abstract":"The rate at which a digital signal processing (DSP) system operates depends on the highest frequency component in the input signal. DSP applications must sample their inputs at a frequency at least twice the highest frequency in the input signal (i.e., the Nyquist rate) to accurately reproduce the signal. Typically a fixed sampling rate, guaranteed to always be high enough, is used. However, an input signal may have periods when the signal has little high frequency content as well as periods of silence. When the input signal has no perceptible high frequency components, the system can reduce its sampling rate, thereby reducing the number of samples processed per second, allowing the CPU speed to be scaled down without reducing output quality. This paper describes how to reduce power consumption in DSP applications by varying the amount of processing based on the input signal, and reports results of experiments with a prototype implementation. Experiments with a prototype show that when the system performs little processing, the added overhead of the variable sampling rate technique increased power consumption. When the system performs more processing, 18 FIR filters per frame, the power consumption was reduced to 40 % of the power required for a static sampling rate, while not reducing sound quality.","PeriodicalId":256018,"journal":{"name":"ISLPED '05. Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005.","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-08-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125878180","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 57

Self-timed circuits for energy harvesting AC power supplies 用于能量收集交流电源的自定时电路

ISLPED '05. Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005. Pub Date : 2005-08-08 DOI: 10.1145/1077603.1077678

J. Siebert, J. Collier, R. Amirtharajah

引用次数: 14

Coordinated, distributed, formal energy management of chip multiprocessors 芯片多处理器协调、分布式、形式化的能量管理

ISLPED '05. Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005. Pub Date : 2005-08-08 DOI: 10.1145/1077603.1077637

Philo Juang, Qiang Wu, L. Peh, M. Martonosi, D. Clark

{"title":"Coordinated, distributed, formal energy management of chip multiprocessors","authors":"Philo Juang, Qiang Wu, L. Peh, M. Martonosi, D. Clark","doi":"10.1145/1077603.1077637","DOIUrl":"https://doi.org/10.1145/1077603.1077637","url":null,"abstract":"Designers are moving toward chip-multiprocessors (CMPs) to leverage application parallelism for higher performance while keeping design complexity under control. However, to date, no power management techniques have been proposed for coordinated power control of multiple processor cores. In this paper, we illustrate how the use of local, per-tile dynamic voltage and frequency scaling (DVFS) techniques can result in tiles counteracting each others' power management policies, significantly hurting chip power-performance. We then propose a coordinated DVFS scheme for CMPs, which eliminates the oscillations and ensures efficient and resilient DVFS control. Specifically, our proposed technique incorporates thread information collected at runtime across the chip. In addition, by extending a control-theoretic local DVFS control technique toward DVFS for chip-multiprocessors, our technique prescribes DVFS settings formally at each tile, thus ensuring stable, distributed, coordinated DVFS control of a CMP. Experimental results show that our technique achieves a 15.5% improvement in energy-delay product over a CMP with no DVFS control, and a 1% improvement in energy-delay product against the latest state-of-the-art local DVFS scheme.","PeriodicalId":256018,"journal":{"name":"ISLPED '05. Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005.","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-08-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134197813","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 99

A low-power, multichannel gated oscillator-based CDR for short-haul applications 低功耗，多通道门控振荡器的CDR短距离应用

ISLPED '05. Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005. Pub Date : 2005-08-08 DOI: 10.1145/1077603.1077631

A. Tajalli, P. Muller, S. M. Atarodi, Y. Leblebici

引用次数: 1

Effectiveness of low power dual-V/sub t/ designs in nano-scale technologies under process parameter variations 工艺参数变化下低功耗双v /sub /设计在纳米技术中的有效性

ISLPED '05. Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005. Pub Date : 2005-08-08 DOI: 10.1145/1077603.1077609

A. Agarwal, Kunhyuk Kang, S. Bhunia, J. D. Gallagher, K. Roy

引用次数: 15

Inter-program optimizations for conserving disk energy 程序间优化，以节省磁盘能量

ISLPED '05. Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005. Pub Date : 2005-08-08 DOI: 10.1145/1077603.1077684

Jerry Hom, U. Kremer

引用次数: 12

A tunable bus encoder for off-chip data buses 片外数据总线的可调总线编码器

ISLPED '05. Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005. Pub Date : 2005-08-08 DOI: 10.1145/1077603.1077680

D. Suresh, B. Agrawal, Jun Yang, W. Najjar

{"title":"A tunable bus encoder for off-chip data buses","authors":"D. Suresh, B. Agrawal, Jun Yang, W. Najjar","doi":"10.1145/1077603.1077680","DOIUrl":"https://doi.org/10.1145/1077603.1077680","url":null,"abstract":"Off-chip buses constitute a significant portion of the total system power in embedded systems. Past research has focused on encoding contiguous bit positions in data values to reduce the transition activity in the off-chip data buses. In this paper, the authors proposed tunable bus encoding (TUBE) scheme to reduce the power consumption in the data buses, which exploits repetition in contiguous as well as non-contiguous bit positions in order to encode data values. Problems of keeping just one control signal for the codec design were also solved. The results were compared with some of the already existing best schemes such as frequent value encoding (FVE) and FV-MSB-LSB encoding schemes. It is found that the scheme achieves an improvement of 21 % on average and up to 28% on some benchmarks over the FVE scheme and up to 84% over unencoded data. In comparison to FV-MSB-LSB encoding scheme, the presented scheme improves the energy savings by 10% on average and up to 21% for some media applications at the expense of minimal 0.45% performance overhead. A hardware design of the codec was presented and a detailed analysis of the hardware overhead in terms of area, delay and energy consumption were provided. It is again found that the codec can be easily implemented in an on-chip memory controller with small area requirement of 0.0521 mm/sup 2/.","PeriodicalId":256018,"journal":{"name":"ISLPED '05. Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005.","volume":"85 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-08-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125001011","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 13

A low-power crossroad switch architecture and its core placement for network-on-chip 片上网络的低功耗交叉交换架构及其核心布局

ISLPED '05. Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005. Pub Date : 2005-08-08 DOI: 10.1145/1077603.1077693

Kuei-Chung Chang, Jih-Sheng Shen, Tien-Fu Chen

引用次数: 19

Energy-aware fetch mechanism: trace cache and BTB customization 能量感知获取机制:跟踪缓存和BTB定制

ISLPED '05. Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005. Pub Date : 2005-08-08 DOI: 10.1145/1077603.1077615

D. Chaver, Miguel A. Rojas, L. Piñuel, M. Prieto, F. Tirado, Michael C. Huang

引用次数: 11

A low-power bus design using joint repeater insertion and coding 采用联合中继器插入和编码的低功耗总线设计

ISLPED '05. Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005. Pub Date : 2005-08-08 DOI: 10.1145/1077603.1077629

S. Sridhara, Naresh R Shanbhag

引用次数: 8