ISLPED '05. Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005.最新文献_第3页

An evaluation of code and data optimizations in the context of disk power reduction 在磁盘功率降低的情况下对代码和数据优化的评估

ISLPED '05. Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005. Pub Date : 2005-08-08 DOI: 10.1145/1077603.1077655

M. Kandemir, S. Son, Guangyu Chen

{"title":"An evaluation of code and data optimizations in the context of disk power reduction","authors":"M. Kandemir, S. Son, Guangyu Chen","doi":"10.1145/1077603.1077655","DOIUrl":"https://doi.org/10.1145/1077603.1077655","url":null,"abstract":"Disk power management is becoming increasingly important in high-end server and cluster type of environments that execute data-intensive applications. While hardware-only approaches (e.g., low-power modes supported by current disks) are successful to a certain extent, one also needs to consider the software side to achieve further energy savings. This paper first demonstrates that conventional data locality oriented code transformations are not sufficient for minimizing disk power consumption. The reason is that these optimizations do not take into account how disk-resident array data are laid out on the disk system, and consequently, fail to increase idle periods of disks, which is the primary metric using which disk power can be reduced. Instead, we propose a disk layout aware application optimization strategy that uses both code restructuring and data layout optimization. Our experimental evaluation with several benchmark codes reveal that the proposed strategy is very successful in reducing disk energy consumption without performing much worse than a pure data locality oriented scheme, as far as execution cycles are concerned. The experiments also show that the benefits coming from our approach increase with the increased number of disks; i.e., it scales very well.","PeriodicalId":256018,"journal":{"name":"ISLPED '05. Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005.","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-08-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115995674","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 11

A probabilistic framework for power-optimal repeater insertion in global interconnects under parameter variations 参数变化下全局互连中功率最优中继器插入的概率框架

ISLPED '05. Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005. Pub Date : 2005-08-08 DOI: 10.1145/1077603.1077639

V. Wason, K. Banerjee

{"title":"A probabilistic framework for power-optimal repeater insertion in global interconnects under parameter variations","authors":"V. Wason, K. Banerjee","doi":"10.1145/1077603.1077639","DOIUrl":"https://doi.org/10.1145/1077603.1077639","url":null,"abstract":"This paper addresses the problem of power dissipation during the buffer insertion phase of interconnect performance optimization in nanometer scale designs taking all significant parameter variations into account. The relative effect of different device, interconnect and environmental variations on delay and different components of power has been studied. A probabilistic framework to optimize buffer-interconnect designs under variations has been presented and results are compared with those obtained through simple deterministic optimization. Also, statistical models for delay and power under parameter variations have been developed using linear regression techniques. Under statistical analysis, both power and performance of buffer-interconnect designs are shown to degrade with increasing amount of variations. Also, % error in power estimation for power-optimal repeater designs is shown to be significant if variations are not taken into account. Furthermore, it has been shown that due to variations, significantly higher penalties in delay are needed to operate at power levels similar to those under no variations. Finally, the percentage savings in total power for a given penalty in delay are shown to improve with increasing amount of parameter variations.","PeriodicalId":256018,"journal":{"name":"ISLPED '05. Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005.","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-08-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122616958","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 15

Bounds on power savings using runtime dynamic voltage scaling: an exact algorithm and a linear-time heuristic approximation 使用运行时动态电压缩放的省电界限:精确算法和线性时间启发式近似

ISLPED '05. Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005. Pub Date : 2005-08-08 DOI: 10.1145/1077603.1077670

Fen Xie, M. Martonosi, S. Malik

引用次数: 43

Joint exploration of architectural and physical design spaces with thermal consideration 结合热因素对建筑和物理设计空间的共同探索

ISLPED '05. Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005. Pub Date : 2005-08-08 DOI: 10.1145/1077603.1077636

Yen-Wei Wu, Chia-Lin Yang, Ping-Hung Yuh, Yao-Wen Chang

引用次数: 27

On-chip digital power supply control for system-on-chip applications 片上数字电源控制系统的片上应用

ISLPED '05. Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005. Pub Date : 2005-08-08 DOI: 10.1145/1077603.1077677

M. Meijer, J. P. D. Gyvez, R. Otten

引用次数: 29

Understanding the energy efficiency of SMT and CMP with multiclustering 了解SMT和CMP的多聚类能效

ISLPED '05. Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005. Pub Date : 2005-08-08 DOI: 10.1145/1077603.1077616

J. Cong, Ashok Jagannathan, Glenn D. Reinman, Y. Tamir

引用次数: 8

Power prediction for Intel XScale/spl reg/ processors using performance monitoring unit events 使用性能监控单元事件预测Intel XScale/spl reg/处理器的功耗

ISLPED '05. Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005. Pub Date : 2005-08-08 DOI: 10.1145/1077603.1077657

Gilberto Contreras, M. Martonosi

引用次数: 279

Design and optimization on dynamic power system for self-powered integrated wireless sensing nodes 自供电集成无线传感节点动态电源系统的设计与优化

ISLPED '05. Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005. Pub Date : 2005-08-08 DOI: 10.1145/1077603.1077675

D. Ma, Janet Roveda, Mohankumar N. Somasundaram, Zongqi Hu

引用次数: 9

Power grid voltage integrity verification 电网电压完整性验证

ISLPED '05. Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005. Pub Date : 2005-08-08 DOI: 10.1145/1077603.1077661

Maha Nizam, F. Najm, A. Devgan

{"title":"Power grid voltage integrity verification","authors":"Maha Nizam, F. Najm, A. Devgan","doi":"10.1145/1077603.1077661","DOIUrl":"https://doi.org/10.1145/1077603.1077661","url":null,"abstract":"Full-chip verification requires one to check if the power grid is safe, i.e., if the voltage drop on the grid does not exceed a certain threshold. The traditional simulation-based solution to this problem is computationally expensive, because of the large variety of possible circuit behaviors that would need to be simulated; it also has the disadvantage that it requires full knowledge of the details of the circuit attached to the grid, thereby precluding early verification of the grid. We propose a power grid verification technique that can be applied before the complete circuit has been designed and without exact knowledge of the circuit currents. We use current constraints, which are upper bound constraints on the currents that can be drawn from the grid, as a way to capture the uncertainty about the circuit details and activity. Based on this, we propose two solution approaches. One approach gives an upper-bound on the worst-case voltage drop at every node of the grid. Another, less expensive approach, applies a sufficient condition (thus, this becomes a conservative approach) to check if the drop on the grid exceeds a given voltage threshold.","PeriodicalId":256018,"journal":{"name":"ISLPED '05. Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005.","volume":"111 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-08-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116231336","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 27

An 8.3GHz dual supply/threshold optimized 32b integer ALU-register file loop in 90nm CMOS 基于90nm CMOS的8.3GHz双电源/阈值优化32b整数alu寄存器文件环路

ISLPED '05. Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005. Pub Date : 2005-08-08 DOI: 10.1145/1077603.1077630

S. Hsu, A. Agarwal, K. Roy, R. Krishnamurthy, S. Borkar

引用次数: 8