ISLPED '05. Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005.最新文献_第2页

Low power SRAM techniques for handheld products 用于手持产品的低功耗SRAM技术

ISLPED '05. Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005. Pub Date : 2005-08-08 DOI: 10.1145/1077603.1077652

R. Islam, A. Brand, Dave Lippincott

引用次数: 16

A GHz-class charge recovery logic 一个ghz级电荷恢复逻辑

ISLPED '05. Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005. Pub Date : 2005-08-08 DOI: 10.1145/1077603.1077627

V. Sathe, M. Papaefthymiou, C. Ziesler

引用次数: 3

Two efficient methods to reduce power and testing time 两种降低功耗和测试时间的有效方法

ISLPED '05. Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005. Pub Date : 2005-08-08 DOI: 10.1145/1077603.1077646

Il-soo Lee, T. Ambler

引用次数: 6

The need for a full-chip and package thermal model for thermally optimized IC designs 对于热优化IC设计的全芯片和封装热模型的需求

ISLPED '05. Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005. Pub Date : 2005-08-08 DOI: 10.1145/1077603.1077662

Wei Huang, Eric Humenay, K. Skadron, M. Stan

{"title":"The need for a full-chip and package thermal model for thermally optimized IC designs","authors":"Wei Huang, Eric Humenay, K. Skadron, M. Stan","doi":"10.1145/1077603.1077662","DOIUrl":"https://doi.org/10.1145/1077603.1077662","url":null,"abstract":"Modeling and analyzing detailed die temperature with a full-chip thermal model at early design stages is important to discover and avoid potential thermal hazards. However, omitting important aspects of package details in a thermal model can result in significant temperature estimation errors. In this paper, we discuss the applications of an existing compact thermal model that models both die and package temperature details. As an example, a thermally self-consistent leakage power calculation of a POWER4-like microprocessor design is presented. We then demonstrate the importance of including detailed package information in the thermal model by several examples considering the impact of thermal interface material (TIM), which glues the die to the heat spreader. The fact that detailed package information is needed to build an accurate compact thermal model implies a design flow, in which the chip- and package-level compact thermal model acts as a convenient medium for more productive collaborations among circuit designers, computer architects and package designers, leading to early and efficient evaluations of different design tradeoffs for an optimal design from a thermal point of view.","PeriodicalId":256018,"journal":{"name":"ISLPED '05. Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005.","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-08-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126167885","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 57

Complexity reduction in an nRERL microprocessor 降低nrel微处理器的复杂性

ISLPED '05. Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005. Pub Date : 2005-08-08 DOI: 10.1145/1077603.1077649

Seokkee Kim, S. Chae

引用次数: 4

Snug set-associative caches. Reducing leakage power while improving performance 舒适的集关联缓存。在提高性能的同时减少泄漏功率

ISLPED '05. Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005. Pub Date : 2005-08-08 DOI: 10.1145/1077603.1077687

Jia-Jhe Li, Yuan-Shin Hwang

{"title":"Snug set-associative caches. Reducing leakage power while improving performance","authors":"Jia-Jhe Li, Yuan-Shin Hwang","doi":"10.1145/1077603.1077687","DOIUrl":"https://doi.org/10.1145/1077603.1077687","url":null,"abstract":"As transistors keep shrinking and on-chip data caches keep growing, static power dissipation due to leakage of caches takes an increasing fraction of total power in processors. Several techniques have already been proposed to reduce leakage power by turning off unused cache lines. However, they all have to pay the price of performance degradation. This paper presents a cache architecture, the snug set-associative (SSA) cache, that does not only cut most of static power dissipation but also reduces execution times. The SSA cache reduces leakage power by implementing the minimum set-associative scheme, which only activates the minimal numbers of ways in each cache set, while the performance losses incurred by this scheme are compensated by the base-offset load/store queues. These two techniques are both developed based on the principle of locality and they work together nicely - experimental results show that the minimum set-associative scheme can cut static power consumption of the L1 data cache by 90% on average for SPECint2000 benchmarks, while the execution times are reduced by 3% when the default 8-entry load/store queue is modified to the base-offset design. Furthermore, the SSA cache can trim the leakage power of L2 data cache by 96% on average while still accomplishing a 3% reduction in execution times.","PeriodicalId":256018,"journal":{"name":"ISLPED '05. Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005.","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-08-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128746686","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 9

Analysis and mitigation of variability in subthreshold design 亚阈值设计中可变性的分析与缓解

ISLPED '05. Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005. Pub Date : 2005-08-08 DOI: 10.1145/1077603.1077610

Bo Zhai, S. Hanson, D. Blaauw, D. Sylvester

{"title":"Analysis and mitigation of variability in subthreshold design","authors":"Bo Zhai, S. Hanson, D. Blaauw, D. Sylvester","doi":"10.1145/1077603.1077610","DOIUrl":"https://doi.org/10.1145/1077603.1077610","url":null,"abstract":"Subthreshold circuit design is a compelling method for ultra-low power applications. However, subthreshold designs show dramatically increased sensitivity to process variations due to the exponential relationship of subthreshold drive current with V/sub th/ variation. In this paper, we present an analysis of subthreshold energy efficiency considering process variation, and propose methods to mitigate its impact. We show that, unlike superthreshold circuits, random dopant fluctuation is the dominant component of variation in subthreshold operation. We investigate how this variability can be ameliorated with proper circuit sizing and choice of circuit logic depth. We then present a statistical analysis of the energy efficiency of subthreshold circuits considering process variations. We show that the energy optimal supply voltage increases due to process variations and study its dependence on circuit parameters. We verify our analytical models against Monte Carlo SPICE simulations and show that they accurately predict the minimum energy and energy optimal supply voltage. Finally, we use the developed statistical energy model to determine the optimal pipelining depth in subthreshold designs.","PeriodicalId":256018,"journal":{"name":"ISLPED '05. Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005.","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-08-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129802906","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 285

Measurements and modeling of intrinsic fluctuations in MOSFET threshold voltage MOSFET阈值电压固有波动的测量和建模

ISLPED '05. Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005. Pub Date : 2005-08-08 DOI: 10.1145/1077603.1077611

A. Keshavarzi, G. Schrom, Stephen Tang, Sean Ma, K. Bowman, S. Tyagi, Kevin Zhang, T. Linton, N. Hakim, S. Duvall, J. Brews, V. De

引用次数: 56

FinFET-based SRAM design 基于finfet的SRAM设计

ISLPED '05. Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005. Pub Date : 2005-08-08 DOI: 10.1145/1077603.1077607

Z. Guo, S. Balasubramanian, R. Zlatanovici, T. King, B. Nikolić

引用次数: 169

An algebraic decision diagram (ADD) based technique to find leakage histograms of combinational designs 基于代数决策图(ADD)的组合设计泄漏直方图查找技术

ISLPED '05. Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005. Pub Date : 2005-08-08 DOI: 10.1145/1077603.1077633

Kanupriya Gulati, N. Jayakumar, S. Khatri

引用次数: 3