Measurements and modeling of intrinsic fluctuations in MOSFET threshold voltage

Abstract

Fluctuations in intrinsic linear V/sub T/, free of impact of parasitics, are measured for large arrays of NMOS and PMOS devices on a testchip in a 150nm logic technology. Local intrinsic /spl rho/V/sub T/, free of extrinsic process, length and width variations, is random, and worsens with reverse body bias. Although the traditional area-dependent component is dominant, a significant component of the fluctuations in small devices depends only on device width or length.