低功耗，多通道门控振荡器的CDR短距离应用

ISLPED '05. Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005. Pub Date : 2005-08-08 DOI:10.1145/1077603.1077631

A. Tajalli, P. Muller, S. M. Atarodi, Y. Leblebici

{"title":"低功耗，多通道门控振荡器的CDR短距离应用","authors":"A. Tajalli, P. Muller, S. M. Atarodi, Y. Leblebici","doi":"10.1145/1077603.1077631","DOIUrl":null,"url":null,"abstract":"A gated current-controlled oscillator (GCCO) based topology is used to implement a low-power multi-channel clock and data recovery (CDR) system in a 0.18/spl mu/m digital CMOS technology. A systematic approach is presented to design a reliable and low-power system based on the required specifications. Behavioral simulations are also used to estimate the achievable bit error rate (BER), jitter tolerance (JTOL), and frequency offset tolerance (FTOL) of the proposed CDR. Using a single 1.8 V supply voltage, the proposed 20Gbps 8-channel CDR consumes only 70.2mW or 3.51 mW/channel/Gbps while occupies 0.045mm/sup 2/ silicon area.","PeriodicalId":256018,"journal":{"name":"ISLPED '05. Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005.","volume":"31 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2005-08-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"A low-power, multichannel gated oscillator-based CDR for short-haul applications\",\"authors\":\"A. Tajalli, P. Muller, S. M. Atarodi, Y. Leblebici\",\"doi\":\"10.1145/1077603.1077631\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A gated current-controlled oscillator (GCCO) based topology is used to implement a low-power multi-channel clock and data recovery (CDR) system in a 0.18/spl mu/m digital CMOS technology. A systematic approach is presented to design a reliable and low-power system based on the required specifications. Behavioral simulations are also used to estimate the achievable bit error rate (BER), jitter tolerance (JTOL), and frequency offset tolerance (FTOL) of the proposed CDR. Using a single 1.8 V supply voltage, the proposed 20Gbps 8-channel CDR consumes only 70.2mW or 3.51 mW/channel/Gbps while occupies 0.045mm/sup 2/ silicon area.\",\"PeriodicalId\":256018,\"journal\":{\"name\":\"ISLPED '05. Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005.\",\"volume\":\"31 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2005-08-08\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"ISLPED '05. Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005.\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1145/1077603.1077631\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"ISLPED '05. Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005.","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1145/1077603.1077631","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 1

摘要

采用基于门控电流控制振荡器(GCCO)的拓扑结构，在0.18/spl mu/m的数字CMOS技术下实现了低功耗多通道时钟和数据恢复(CDR)系统。提出了一种系统的方法，根据要求设计一个可靠的低功耗系统。行为模拟还用于估计CDR的可实现误码率(BER)、抖动容限(JTOL)和频偏容限(FTOL)。使用单个1.8 V电源电压，所提出的20Gbps 8通道CDR仅消耗70.2mW或3.51 mW/通道/Gbps，而占用0.045mm/sup 2/硅面积。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

查看原文本刊更多论文

A low-power, multichannel gated oscillator-based CDR for short-haul applications

A gated current-controlled oscillator (GCCO) based topology is used to implement a low-power multi-channel clock and data recovery (CDR) system in a 0.18/spl mu/m digital CMOS technology. A systematic approach is presented to design a reliable and low-power system based on the required specifications. Behavioral simulations are also used to estimate the achievable bit error rate (BER), jitter tolerance (JTOL), and frequency offset tolerance (FTOL) of the proposed CDR. Using a single 1.8 V supply voltage, the proposed 20Gbps 8-channel CDR consumes only 70.2mW or 3.51 mW/channel/Gbps while occupies 0.045mm/sup 2/ silicon area.

求助全文

通过发布文献求助，成功后即可免费获取论文全文。去求助

来源期刊

ISLPED '05. Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005.

自引率

0.00%

发文量