IEEE/ACM International Conference on Computer Aided Design, 2004. ICCAD-2004.最新文献_第3页

Cost-effective radiation hardening technique for combinational logic 组合逻辑的高性价比辐射硬化技术

IEEE/ACM International Conference on Computer Aided Design, 2004. ICCAD-2004. Pub Date : 2004-11-07 DOI: 10.1109/iccad.2004.1382551

Q. Zhou, K. Mohanram

引用次数: 100

Stochastic analysis of interconnect performance in the presence of process variations 存在工艺变化时互连性能的随机分析

IEEE/ACM International Conference on Computer Aided Design, 2004. ICCAD-2004. Pub Date : 2004-11-07 DOI: 10.1109/ICCAD.2004.1382698

Janet Roveda, P. Ghanta, S. Vrudhula

{"title":"Stochastic analysis of interconnect performance in the presence of process variations","authors":"Janet Roveda, P. Ghanta, S. Vrudhula","doi":"10.1109/ICCAD.2004.1382698","DOIUrl":"https://doi.org/10.1109/ICCAD.2004.1382698","url":null,"abstract":"Deformations in interconnect due to process variations can lead to significant performance degradation in deep sub-micron circuits. Timing analyzers attempt to capture the effects of variation on delay with simplified models. The timing verification of RC or RLC networks requires the substitution of such simplified models with spatial stochastic processes that capture the random nature of process variations. The present work proposes a new and viable method to compute the stochastic response of interconnects. The technique models the stochastic response in an infinite dimensional Hilbert space in terms of orthogonal polynomial expansions. A finite representation is obtained by using the Galerkin approach of minimizing the Hilbert space norm of the residual error. The key advance of the proposed method is that it provides a functional representation of the response of the system in terms of the random variables that represent the process variations. The proposed algorithm has been implemented in a procedure called OPERA, results from OPERA simulations on commercial design test cases match well with those from the classical Monte Carlo SPICE simulations and from perturbation methods. Additionally OPERA shows good computational efficiency: speedup factor of 60 has been observed over Monte Carlo SPICE simulations.","PeriodicalId":255227,"journal":{"name":"IEEE/ACM International Conference on Computer Aided Design, 2004. ICCAD-2004.","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126132186","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 90

Improving soft-error tolerance of FPGA configuration bits 提高FPGA配置位的软容错性

IEEE/ACM International Conference on Computer Aided Design, 2004. ICCAD-2004. Pub Date : 2004-11-07 DOI: 10.1109/ICCAD.2004.1382552

S. Srinivasan, Aman Gayasen, N. Vijaykrishnan, M. Kandemir, Yuan Xie, M. J. Irwin

引用次数: 75

Efficient SAT-based unbounded symbolic model checking using circuit cofactoring 基于sat的无界符号模型的高效电路协分解检验

IEEE/ACM International Conference on Computer Aided Design, 2004. ICCAD-2004. Pub Date : 2004-11-07 DOI: 10.1109/ICCAD.2004.1382631

Malay K. Ganai, Aarti Gupta, P. Ashar

{"title":"Efficient SAT-based unbounded symbolic model checking using circuit cofactoring","authors":"Malay K. Ganai, Aarti Gupta, P. Ashar","doi":"10.1109/ICCAD.2004.1382631","DOIUrl":"https://doi.org/10.1109/ICCAD.2004.1382631","url":null,"abstract":"We describe an efficient approach for SAT-based quantifier elimination that significantly improves the performance of pre-image and fixed-point computation in SAT-based unbounded symbolic model checking (UMC). The proposed method captures a larger set of new states per SAT-based enumeration step during quantifier elimination, in comparison to previous approaches. The novelty of our approach is in the use of circuit-based cofactoring to capture a large set of states, and in the use of a functional hashing based simplified circuit graph to represent the captured states. We also propose a number of heuristics to further enlarge the state set represented per enumeration, thereby reducing the number of enumeration steps. We have implemented our techniques in a SAT-based UMC framework where we show the effectiveness of SAT-based existential quantification on public benchmarks, and on a number of large industry designs that were hard to model check using purely BDD-based techniques. We show several orders of improvement in time and space using our approach over previous CNF-based approaches. We also present controlled experiments to demonstrate the role of several heuristics proposed in the paper. Importantly, we were able to prove using our method the correctness of a safety property in an industry design that could not be proved using other known approaches.","PeriodicalId":255227,"journal":{"name":"IEEE/ACM International Conference on Computer Aided Design, 2004. ICCAD-2004.","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125653397","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 88

Accurate estimation of global buffer delay within a floorplan 准确估计一个平面图内的全局缓冲延迟

IEEE/ACM International Conference on Computer Aided Design, 2004. ICCAD-2004. Pub Date : 2004-11-07 DOI: 10.1109/ICCAD.2004.1382667

C. Alpert, Jiang Hu, S. Sapatnekar, C. Sze

引用次数: 34

Reducing cache misses by application-specific re-configurable indexing 通过特定于应用程序的可重新配置索引减少缓存丢失

IEEE/ACM International Conference on Computer Aided Design, 2004. ICCAD-2004. Pub Date : 2004-11-07 DOI: 10.1109/ICCAD.2004.1382556

Kimish Patel, E. Macii, L. Benini, M. Poncino

引用次数: 21

On per-test fault diagnosis using the X-fault model 基于x故障模型的每次测试故障诊断

IEEE/ACM International Conference on Computer Aided Design, 2004. ICCAD-2004. Pub Date : 2004-11-07 DOI: 10.1109/ICCAD.2004.1382653

X. Wen, T. Miyoshi, S. Kajihara, Laung-Terng Wang, K. Saluja, K. Kinoshita

引用次数: 34

Robust analog/RF circuit design with projection-based posynomial modeling 基于投影多项式建模的鲁棒模拟/射频电路设计

IEEE/ACM International Conference on Computer Aided Design, 2004. ICCAD-2004. Pub Date : 2004-11-07 DOI: 10.1109/ICCAD.2004.1382694

Xin Li, P. Gopalakrishnan, Yang Xu, L. Pileggi

引用次数: 68

Best practices in low power design. 1. Power reduction techniques [Tutorial 1] 低功耗设计的最佳实践。1. 节能技术[教程1]

IEEE/ACM International Conference on Computer Aided Design, 2004. ICCAD-2004. Pub Date : 2004-11-07 DOI: 10.1109/ICCAD.2004.1382523

E. Mocii, Massoud Pedram

{"title":"Best practices in low power design. 1. Power reduction techniques [Tutorial 1]","authors":"E. Mocii, Massoud Pedram","doi":"10.1109/ICCAD.2004.1382523","DOIUrl":"https://doi.org/10.1109/ICCAD.2004.1382523","url":null,"abstract":"Description: In the last decade, huge effort has been invested to come up with a wide range of design solutions that help in solving the power consumption problem for different types of electronic devices, components and systems. Some of those solutions turned out to be very practical and effective, thus finding a path into commercial products of a different nature. Other approaches, which sounded promising on paper, showed too many limitations for attracting the attention of real designers. The objective of this tutorial is to offer the attendees some wellestablished, yet innovative recipes for addressing the power problem in real life. The presentation will be structured into two half-day tutorials. The moming tutorial will describe basic techniques, applicable at different levels of abstraction, that have proven to hold great potential for power optimization in practical design environments. They range from RTL power management and clock-tree architecture design to memory and bus interface design. Also some of the latest solutions regarding frequency and voltage dynamic control, as well as solutions for leakage power management will be discussed.","PeriodicalId":255227,"journal":{"name":"IEEE/ACM International Conference on Computer Aided Design, 2004. ICCAD-2004.","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129193689","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

Code partitioning for synthesis of embedded applications with phantom 用幻影合成嵌入式应用程序的代码划分

IEEE/ACM International Conference on Computer Aided Design, 2004. ICCAD-2004. Pub Date : 2004-11-07 DOI: 10.1109/ICCAD.2004.1382569

A. C. Nacul, T. Givargis

{"title":"Code partitioning for synthesis of embedded applications with phantom","authors":"A. C. Nacul, T. Givargis","doi":"10.1109/ICCAD.2004.1382569","DOIUrl":"https://doi.org/10.1109/ICCAD.2004.1382569","url":null,"abstract":"In a large class of embedded systems, dynamic multitasking using traditional OS techniques is infeasible because of memory and processing overheads or lack of operating systems availability for the target embedded processor. Serializing compilers have been proposed as an alternative solution, enabling a designer to develop multitasking applications without the need of OS support. A serializing compiler is a source-to-source translator that takes a POSIX compliant multitasking C program as input and generates an equivalent, embedded processor independent, single-threaded ANSI C program, to be compiled using the embedded processor-specific tool chain. Such serializing compilers work by partitioning each task into blocks of code and synthesizing a scheduler that dynamically switches among these blocks. The quality of the compiled code in terms of multitasking overhead and task latency is highly dependent on the partitioning algorithm. In this work, we give our solution to the partitioning problem in the context of serializing compilers. We show that it is possible to provide the designer with a set of Pareto-optimal solutions that trade off multitasking overhead for task latency.","PeriodicalId":255227,"journal":{"name":"IEEE/ACM International Conference on Computer Aided Design, 2004. ICCAD-2004.","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134377765","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 18