IEEE/ACM International Conference on Computer Aided Design, 2004. ICCAD-2004.最新文献

Efficient computation of small abstraction refinements 小抽象细化的高效计算

IEEE/ACM International Conference on Computer Aided Design, 2004. ICCAD-2004. Pub Date : 2004-11-07 DOI: 10.1109/ICCAD.2004.1382632

Bing Li, F. Somenzi

引用次数: 9

A flexibility aware budgeting for hierarchical flow timing closure 一种灵活的分级流时序封闭预算

IEEE/ACM International Conference on Computer Aided Design, 2004. ICCAD-2004. Pub Date : 2004-11-07 DOI: 10.1109/ICCAD.2004.1382583

O. Omedes, M. Robert, M. Ramdani

引用次数: 2

Incremental deductive & inductive reasoning for SAT-based bounded model checking 基于sat的有界模型检验的增量演绎和归纳推理

IEEE/ACM International Conference on Computer Aided Design, 2004. ICCAD-2004. Pub Date : 2004-11-07 DOI: 10.1109/ICCAD.2004.1382630

Liang Zhang, M. Prasad, M. Hsiao

引用次数: 28

Static statistical timing analysis for latch-based pipeline designs 基于锁存器的管道设计静态统计时序分析

IEEE/ACM International Conference on Computer Aided Design, 2004. ICCAD-2004. Pub Date : 2004-11-07 DOI: 10.1109/ICCAD.2004.1382622

Rob A. Rutenbar, Li-C. Wang, K. Cheng, S. Kundu

引用次数: 32

Analog performance space exploration by Fourier-Motzkin elimination with application to hierarchical sizing 傅立叶-莫兹金消去法在分级分级中的应用

IEEE/ACM International Conference on Computer Aided Design, 2004. ICCAD-2004. Pub Date : 2004-11-07 DOI: 10.1109/ICCAD.2004.1382693

G. Stehr, H. Graeb, K. Antreich

引用次数: 20

Dynamic voltage and frequency scaling under a precise energy model considering variable and fixed components of the system power dissipation 考虑系统功耗的可变和固定分量的精确能量模型下的动态电压和频率缩放

IEEE/ACM International Conference on Computer Aided Design, 2004. ICCAD-2004. Pub Date : 2004-11-07 DOI: 10.1109/ICCAD.2004.1382538

Kihwan Choi, Wonbok Lee, R. Soma, Massoud Pedram

引用次数: 74

Gate sizing for crosstalk reduction under timing constraints by Lagrangian relaxation 拉格朗日弛豫约束下串扰减小的栅极尺寸

IEEE/ACM International Conference on Computer Aided Design, 2004. ICCAD-2004. Pub Date : 2004-11-07 DOI: 10.1109/ICCAD.2004.1382535

D. Sinha, H. Zhou

引用次数: 25

A new incremental placement algorithm and its application to congestion-aware divisor extraction 一种新的增量布局算法及其在拥堵感知除数提取中的应用

IEEE/ACM International Conference on Computer Aided Design, 2004. ICCAD-2004. Pub Date : 2004-11-07 DOI: 10.1109/ICCAD.2004.1382637

S. Chatterjee, R. Brayton

{"title":"A new incremental placement algorithm and its application to congestion-aware divisor extraction","authors":"S. Chatterjee, R. Brayton","doi":"10.1109/ICCAD.2004.1382637","DOIUrl":"https://doi.org/10.1109/ICCAD.2004.1382637","url":null,"abstract":"This work presents two contributions. The first is an incremental placement algorithm for placement-aware logic synthesis along with a proof of optimality. The algorithm can efficiently compute the optimum location for a newly introduced node in a network that minimizes the incremental increase in the total half-perimeter wire-length of the network. The algorithm can be applied in a variety of placement-aware optimization contexts. The second contribution is a specific application of this algorithm to placement-aware common divisor extraction. We evaluate the effectiveness of the proposed extraction procedure by using it in an otherwise non-placement-aware flow with two different final placers. The first flow uses an industrial congestion-driven placer and results in an average reduction of 21% in congestion as measured by the global router. The second flow uses an academic wire-length-driven placer and results in an average reduction of 11% for a tool-specific measure of congestion estimated from the placement. Our experiments also reveal a rather surprising phenomenon: in many cases the attempt to minimize the wire-length results in fewer literals after extraction than with a conventional literal-driven approach.","PeriodicalId":255227,"journal":{"name":"IEEE/ACM International Conference on Computer Aided Design, 2004. ICCAD-2004.","volume":"56 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126880306","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 9

Sparse and efficient reduced order modeling of linear subcircuits with large number of terminals 具有大量终端的线性子电路的稀疏高效降阶建模

IEEE/ACM International Conference on Computer Aided Design, 2004. ICCAD-2004. Pub Date : 2004-11-07 DOI: 10.1109/ICCAD.2004.1382548

P. Feldmann, Frank Liu

{"title":"Sparse and efficient reduced order modeling of linear subcircuits with large number of terminals","authors":"P. Feldmann, Frank Liu","doi":"10.1109/ICCAD.2004.1382548","DOIUrl":"https://doi.org/10.1109/ICCAD.2004.1382548","url":null,"abstract":"In the process of designing state-of-the art VLSI circuit we often encounter large but highly structured linear subcircuits with large number of terminals. Classical examples are power supply networks, clock distribution networks, large data buses, etc. Various applications would benefit from efficient high level models of such networks. Unfortunately the existing model-order-reduction algorithms are not adapted to handle more than a few tens of terminals. This talk introduces RecMOR, an algorithm for the computation of reduced order models of structured linear circuits with numerous I/O ports. The algorithm exploits certain regularities of the subcircuit response that are typical in numerous applications of interest. When these regularities are present, the normally dense matrix-transfer function of the subcircuit contains sub-blocks that in some sense are significantly low rank and can be compactly modeled by the recently introduced SVDMOR algorithm. The new RecMOR algorithm decomposes the large matrix-transfer function recursively, and applies SVDMOR compression adaptively to the sub-blocks of the transfer function. The result is a reduced order model that is sparse, efficient, and directly usable as an efficient substitute of the subcircuit in circuit simulations. The method is illustrated on several circuit examples.","PeriodicalId":255227,"journal":{"name":"IEEE/ACM International Conference on Computer Aided Design, 2004. ICCAD-2004.","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114534508","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 98

Delay noise pessimism reduction by logic correlations 通过逻辑关联降低延迟噪声悲观

IEEE/ACM International Conference on Computer Aided Design, 2004. ICCAD-2004. Pub Date : 2004-11-07 DOI: 10.1109/ICCAD.2004.1382564

A. Glebov, S. Gavrilov, R. Soloviev, V. Zolotov, M. Becer, C. Oh, R. Panda

{"title":"Delay noise pessimism reduction by logic correlations","authors":"A. Glebov, S. Gavrilov, R. Soloviev, V. Zolotov, M. Becer, C. Oh, R. Panda","doi":"10.1109/ICCAD.2004.1382564","DOIUrl":"https://doi.org/10.1109/ICCAD.2004.1382564","url":null,"abstract":"High-performance digital circuits are facing increasingly severe signal integrity problems due to crosstalk noise and therefore the state-of-the-art static timing analysis (STA) methods consider crosstalk-induced delay variation. Current noise-aware STA methods compute noise-induced delay uncertainty for each net independently and annotate appropriate delay changes of nets onto data paths and associated clock paths to determine timing violations. Since delay changes in individual nets contribute cumulatively to delay changes of paths, even small amounts of pessimism in noise computation of nets can add up to produce large timing violations for paths, which may be unrealistic. Unlike glitch noise analysis where noise often attenuates during propagation, quality of delay noise analysis is severely affected by any pessimism in noise estimation and can unnecessarily cost valuable silicon and design resources for fixing unreal violations. In this paper, we propose a method to reduce pessimism in noise-aware STA by considering signal correlations of all nets associated with an entire timing path simultaneously, in a path-based approach. We first present an exact algorithm based on the branch-and-bound technique and then extend it with several heuristic techniques so that very large industrial designs can be analyzed efficiently. These techniques, which are implemented in an industrial crosstalk noise analysis tool, show as much as 75% reduction in the computed path delay variations.","PeriodicalId":255227,"journal":{"name":"IEEE/ACM International Conference on Computer Aided Design, 2004. ICCAD-2004.","volume":"228 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116196723","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 15