IEEE/ACM International Conference on Computer Aided Design, 2004. ICCAD-2004.最新文献

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Theoretical framework for compositional sequential hardware equivalence verification in presence of design constraints 存在设计约束的组合顺序硬件等效验证的理论框架
IEEE/ACM International Conference on Computer Aided Design, 2004. ICCAD-2004. Pub Date : 2004-11-07 DOI: 10.1109/ICCAD.2004.1382543
Z. Khasidashvili, Marcelo Skaba, Daher Kaiss, Z. Hanna
{"title":"Theoretical framework for compositional sequential hardware equivalence verification in presence of design constraints","authors":"Z. Khasidashvili, Marcelo Skaba, Daher Kaiss, Z. Hanna","doi":"10.1109/ICCAD.2004.1382543","DOIUrl":"https://doi.org/10.1109/ICCAD.2004.1382543","url":null,"abstract":"We are interested in sequential hardware equivalence (or alignability equivalence) verification of synchronous sequential circuits as stated in C. Pixley (1992). To cope with large industrial designs, the circuits must be divided into smaller subcircuits and verified separately. Furthermore, in order to succeed in verifying the subcircuits, design constraints must be added to the subcircuits. These constraints mimic \"essential\" behavior of the subcircuit environment. In this work, we extend the classical alignability theory in the presence of design constraints, and prove a compositionality result allowing inferring alignability of the circuits from alignability of the subcircuits. As a result, we build a divide and conquer framework for alignability verification. This framework is successfully used on Intel designs.","PeriodicalId":255227,"journal":{"name":"IEEE/ACM International Conference on Computer Aided Design, 2004. ICCAD-2004.","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129176671","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 24
Variability in sub-100nm SRAM designs 100nm以下SRAM设计的可变性
IEEE/ACM International Conference on Computer Aided Design, 2004. ICCAD-2004. Pub Date : 2004-11-07 DOI: 10.1109/ICCAD.2004.1382599
R. Heald, Ping-Wei Wang
{"title":"Variability in sub-100nm SRAM designs","authors":"R. Heald, Ping-Wei Wang","doi":"10.1109/ICCAD.2004.1382599","DOIUrl":"https://doi.org/10.1109/ICCAD.2004.1382599","url":null,"abstract":"Many components of variability become larger percentage design factors with decreasing feature size. Hence, the small transistors in SRAM cells are particularly sensitive to these variations. The SRAM cell transistors in sub-100-nm designs may contain fewer than 100 channel dopant atoms. To achieve a robust design with such variability, one must enhance the normal static-noise-margin and write-trip-point analysis, often with Monte Carlo simulations using statistical transistor models including the process and mismatch fluctuations. Similar challenges exist for the sense amplifiers normally used with SRAM arrays. Except with very low speed designs, yield to speed can be substantially reduced by variations between nominally matched sense amplifier transistors as well as by the variability resulting in a very worst memory cell low read current. This also increases the hazards of delay timing with dummy paths and dummy cells and increases the need for at-speed testing prior to repair.","PeriodicalId":255227,"journal":{"name":"IEEE/ACM International Conference on Computer Aided Design, 2004. ICCAD-2004.","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130814393","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 154
Variational interconnect analysis via PMTBR 基于PMTBR的变分互连分析
IEEE/ACM International Conference on Computer Aided Design, 2004. ICCAD-2004. Pub Date : 2004-11-07 DOI: 10.1109/ICCAD.2004.1382697
J. Phillips
{"title":"Variational interconnect analysis via PMTBR","authors":"J. Phillips","doi":"10.1109/ICCAD.2004.1382697","DOIUrl":"https://doi.org/10.1109/ICCAD.2004.1382697","url":null,"abstract":"We demonstrate an algorithm for interconnect modeling in the presence of process variation based on extension of the truncated balanced realization model reduction algorithm to multi-dimensional, parameter varying systems. Our scheme, based on a set of estimators of the variational TBR projection spaces, is simple to implement, contains embedded error estimators, and leads to nearly optimally sized models.","PeriodicalId":255227,"journal":{"name":"IEEE/ACM International Conference on Computer Aided Design, 2004. ICCAD-2004.","volume":"556 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132479046","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 77
Interconnect lifetime prediction under dynamic stress for reliability-aware design 动态应力下互连寿命预测的可靠性感知设计
IEEE/ACM International Conference on Computer Aided Design, 2004. ICCAD-2004. Pub Date : 2004-11-07 DOI: 10.1109/ICCAD.2004.1382595
Zhijian Lu, Wei Huang, J. Lach, M. Stan, K. Skadron
{"title":"Interconnect lifetime prediction under dynamic stress for reliability-aware design","authors":"Zhijian Lu, Wei Huang, J. Lach, M. Stan, K. Skadron","doi":"10.1109/ICCAD.2004.1382595","DOIUrl":"https://doi.org/10.1109/ICCAD.2004.1382595","url":null,"abstract":"Thermal effects are becoming a limiting factor in high-performance circuit design due to the strong temperature-dependence of leakage power, circuit performance, IC package cost and reliability. While many interconnect reliability models assume a constant temperature, this paper presents a physics-based model for estimating interconnect lifetime for any time-varying temperature/current profile. This model is verified with numerical solutions. With this model, we show that designers may be more aggressive with the temperature profiles that are allowed on a chip. In fact, our model reveals that when the temperature magnitude variation is small, average temperature (instead of worst-case temperature) can be used to accurately predict interconnect lifetime, allowing for significant design margin reclamation in reliability-aware design. Even when the variation of temperature magnitude is large, our model shows that using the maximum temperature is still too conservative for interconnect lifetime prediction. Therefore, our model not only increases the accuracy of reliability estimates, but also enables designers to consider more aggressive designs. This model is similarly useful for temperature-aware dynamic runtime management.","PeriodicalId":255227,"journal":{"name":"IEEE/ACM International Conference on Computer Aided Design, 2004. ICCAD-2004.","volume":"65 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127110265","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 78
Simultaneous design and placement of multiplexed chemical processing systems on microchips 在微芯片上同时设计和放置多路化学处理系统
IEEE/ACM International Conference on Computer Aided Design, 2004. ICCAD-2004. Pub Date : 2004-11-07 DOI: 10.1109/ICCAD.2004.1382577
A. Pfeiffer, T. Mukherjee, S. Hauan
{"title":"Simultaneous design and placement of multiplexed chemical processing systems on microchips","authors":"A. Pfeiffer, T. Mukherjee, S. Hauan","doi":"10.1109/ICCAD.2004.1382577","DOIUrl":"https://doi.org/10.1109/ICCAD.2004.1382577","url":null,"abstract":"Microchip structures represent an attractive platform for microscale chemical processing of fluidic systems. However, standardized design methods for these devices have not yet been developed. Here we describe our work toward adapting traditional SoC circuit design techniques for the synthesis of fully customized and multiplexed lab-on-a-chip (LoC) devices. We discuss our formulation of the multiplex layout problem and present an approach for the design of microchip based electrophoretic separation systems. This work is extendable to systems incorporating mixing and reaction.","PeriodicalId":255227,"journal":{"name":"IEEE/ACM International Conference on Computer Aided Design, 2004. ICCAD-2004.","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129096986","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
Optimizing mode transition sequences in idle intervals for component-level and system-level energy minimization 优化模式转换序列在空闲时间的组件级和系统级的能量最小化
IEEE/ACM International Conference on Computer Aided Design, 2004. ICCAD-2004. Pub Date : 2004-11-07 DOI: 10.1109/ICCAD.2004.1382537
Jinfeng Liu, P. Chou
{"title":"Optimizing mode transition sequences in idle intervals for component-level and system-level energy minimization","authors":"Jinfeng Liu, P. Chou","doi":"10.1109/ICCAD.2004.1382537","DOIUrl":"https://doi.org/10.1109/ICCAD.2004.1382537","url":null,"abstract":"New embedded systems offer rich power management features in the form of multiple operational and nonoperational power modes. While they offer mechanisms for better energy efficiency, they also complicate power management decisions in the presence of realtime constraints. A traditional dynamic power management techniques based on localized break-even-time analysis with simple on/off power controls often yield suboptimal if not incorrect results globally. To address these problems, This work presents two core algorithms for reducing idle energy consumption at the component level and system level. The first algorithm discovers the optimal sequence for mode transition over multiple power modes under timing constraints. It assists the second algorithm that performs a sophisticated global search strategy to aggressively explore system-wide energy savings by correctly interpreting the constraints across all subsystems. Experimental results show that in an embedded radio system where idle energy cost matches or exceeds the active energy consumption, our technique can further reduce the idle energy by 50-70%, which translates into 30-50% of overall system energy compared to existing techniques.","PeriodicalId":255227,"journal":{"name":"IEEE/ACM International Conference on Computer Aided Design, 2004. ICCAD-2004.","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128964608","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 16
The impact of device parameter variations on the frequency and performance of VLSI chips 器件参数变化对VLSI芯片频率和性能的影响
IEEE/ACM International Conference on Computer Aided Design, 2004. ICCAD-2004. Pub Date : 2004-11-07 DOI: 10.1109/ICCAD.2004.1382598
Samie B Samaan
{"title":"The impact of device parameter variations on the frequency and performance of VLSI chips","authors":"Samie B Samaan","doi":"10.1109/ICCAD.2004.1382598","DOIUrl":"https://doi.org/10.1109/ICCAD.2004.1382598","url":null,"abstract":"The distance-correlated (continuous) within-die (WID) process variations of transistor parameters appears to be approximately scaling with process generations. Furthermore, shrinking clock cycles and the scaling of functional block dimensions in complex chips (e.g. CPUs), cause a shortening of interconnect distances. These effects mitigate correlated variations' impact on delay changes across a die. Temperature has a small effect, and supply distribution can be well-understood and designed. Furthermore, uncorrelated (random) variations (e.g. RDF, & LER) currently have a small impact on speed-setting paths, and even multiplying their effect (as processes shrink), would not make them very significant. Coupled with methods for estimating the shift in the maximum operating frequency (F/sub max/) of a die (due to variations), it is shown that variations will continue to have a small effect on product speeds through the mid-term future.","PeriodicalId":255227,"journal":{"name":"IEEE/ACM International Conference on Computer Aided Design, 2004. ICCAD-2004.","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129768322","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 51
Efficient statistical timing analysis through error budgeting 通过误差预算进行有效的统计时间分析
IEEE/ACM International Conference on Computer Aided Design, 2004. ICCAD-2004. Pub Date : 2004-11-07 DOI: 10.1109/ICCAD.2004.1382623
Vishal Khandelwal, A. Davoodi, Ankur Srivastava
{"title":"Efficient statistical timing analysis through error budgeting","authors":"Vishal Khandelwal, A. Davoodi, Ankur Srivastava","doi":"10.1109/ICCAD.2004.1382623","DOIUrl":"https://doi.org/10.1109/ICCAD.2004.1382623","url":null,"abstract":"We propose a technique for optimizing the runtime in statistical timing analysis. Given a global acceptable error budget at the primary output which signifies the difference in the area of the accurate and approximate timing CDFs, we propose a formulation of budgeting this global error across all nodes in the circuit. This node error budget is used to simplify the computation of arrival time CDFs at each node using approximations. This simplification reduces the runtime of statistical timing analysis. We investigate two ways of exploiting this node error budget, firstly through piecewise linear approximation (see ibid., A. Devgan and C. Kashyap, 2003) and secondly though hierarchical quadratic approximation. Experimental results on ISCAS/MCNC benchmarks show that our approach is at most 3 times faster than accurate statistical timing analysis and had a very small error. We also found quadratic piecewise approximation to be more accurate than linear approximation but at lesser gains in runtime.","PeriodicalId":255227,"journal":{"name":"IEEE/ACM International Conference on Computer Aided Design, 2004. ICCAD-2004.","volume":"311 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132824262","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 16
Detection of multiple transitions in delay fault test of SPARC64 microprocessor SPARC64微处理器延迟故障测试中多个过渡的检测
IEEE/ACM International Conference on Computer Aided Design, 2004. ICCAD-2004. Pub Date : 2004-11-07 DOI: 10.1109/ICCAD.2004.1382701
D. Maruyama, A. Kanuma, T. Mochiyama, H. Komatsu, Yaroku Sugiyama, N. Ito
{"title":"Detection of multiple transitions in delay fault test of SPARC64 microprocessor","authors":"D. Maruyama, A. Kanuma, T. Mochiyama, H. Komatsu, Yaroku Sugiyama, N. Ito","doi":"10.1109/ICCAD.2004.1382701","DOIUrl":"https://doi.org/10.1109/ICCAD.2004.1382701","url":null,"abstract":"This work presents a new non-robust delay fault test generation method for the purpose of screening delay defects of microprocessors with fewer test vectors. It is important to reduce the number of test vectors in order to reduce test time, memory usage in the tester, and the overall testing cost. By paying attention to the constraints of off-path inputs in a non-robust test, we made it possible to generate a pair of test vectors to detect multiple delay faults based on the traditional dynamic compaction technique. Delay fault test based on our method is applied to SPARC64 microprocessor with 1.3 GHz clock for screening delay defects, and we achieved 90% coverage with 3,567 test vectors. The comparison results also show that the robust test is not practical for the screening purpose, since it needs more than three times the number of test vectors as compared to the non-robust test.","PeriodicalId":255227,"journal":{"name":"IEEE/ACM International Conference on Computer Aided Design, 2004. ICCAD-2004.","volume":"115 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122422006","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Hybrid techniques for electrostatic analysis of nanowires 纳米线静电分析的混合技术
IEEE/ACM International Conference on Computer Aided Design, 2004. ICCAD-2004. Pub Date : 2004-11-07 DOI: 10.1109/ICCAD.2004.1382579
Gang Li, N. Aluru
{"title":"Hybrid techniques for electrostatic analysis of nanowires","authors":"Gang Li, N. Aluru","doi":"10.1109/ICCAD.2004.1382579","DOIUrl":"https://doi.org/10.1109/ICCAD.2004.1382579","url":null,"abstract":"We propose an efficient approach, namely the hybrid BIE/Poisson/Schrodinger approach, for electrostatic analysis of nanowires. In this approach, the interior and the exterior domain electrostatics are described by Poisson's equation (or Poisson's equation coupled with Schrodinger's equation when quantum-mechanical effects are dominant) and the boundary integral formulation of the potential equation, respectively. We employ a meshless finite cloud method and a boundary cloud method to solve the coupled equations self-consistently. The proposed approach significantly reduces the computational cost and provides a higher accuracy of the solution.","PeriodicalId":255227,"journal":{"name":"IEEE/ACM International Conference on Computer Aided Design, 2004. ICCAD-2004.","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128254778","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
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