IEEE/ACM International Conference on Computer Aided Design, 2004. ICCAD-2004.最新文献

{"title":"Power estimation for cycle-accurate functional descriptions of hardware","authors":"Lin Zhong, S. Ravi, A. Raghunathan, N. Jha","doi":"10.1109/ICCAD.2004.1382659","DOIUrl":"https://doi.org/10.1109/ICCAD.2004.1382659","url":null,"abstract":"Cycle-accurate functional descriptions (CAFD) are being widely adopted in integrated circuit (IC) design flows. Power estimation can potentially benefit from the inherent increase in simulation efficiency of cycle-based functional simulation. Currently, most approaches to hardware power estimation operate at the register-transfer level (RTL), or lower levels of design abstraction. Attempts at power estimation for functional descriptions have suffered from poor accuracy because the design decisions performed during their synthesis lead to an unavoidable, large uncertainty in any power estimate that is based solely on the functional description. We propose a methodology for CAFD power estimation that combines the accuracy achieved by power estimation at the structural RTL with the efficiency of cycle-accurate functional simulation. We achieve this goal by viewing a CAFD as an abstraction of a specific, known RTL implementation that is synthesized from it. We identify correlations between a CAFD and its RTL implementation, and \"back-annotate\" information into the CAFD solely for the purpose of power estimation. The resulting RTL-aware CAFD contains a layer of code that instantiates virtual placeholders for RTL components, and maps values of CAFD variables into the RTL components' inputs/outputs, thus enabling efficient and accurate power estimation. Power estimation is performed in our methodology by simply co-simulating the RTL-aware CAFD with a simulatable power model library that contains power macro-models for each RTL component. We present techniques to further improve the speed of CAFD power estimation, through the use of control state-based adaptive power sampling. We have implemented and evaluated the proposed techniques in the context of a commercial C-based hardware design flow. Experiments with a number of large industrial designs (up to 1 million gates) demonstrate that the proposed methodology achieves accuracy very close to RTL power estimation with two-to-three orders of magnitude speedup in estimation times.","PeriodicalId":255227,"journal":{"name":"IEEE/ACM International Conference on Computer Aided Design, 2004. ICCAD-2004.","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133789016","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Unification of partitioning, placement and floorplanning","authors":"Saurabh N. Adya, Shubhyant Chaturvedi, Jarrod A. Roy, D. Papa, I. Markov","doi":"10.1109/ICCAD.2004.1382639","DOIUrl":"https://doi.org/10.1109/ICCAD.2004.1382639","url":null,"abstract":"Large macro blocks, pre-designed datapaths, embedded memories and analog blocks are increasingly used in ASIC designs. However, robust algorithms for large-scale placement of such designs have only recently been considered in the literature, and improvements by over 10% per paper are still common. Large macros can be handled by traditional floorplanning, but are harder to account for in min-cut and analytical placement. On the other hand, traditional floorplanning techniques do not scale to large numbers of objects, especially in terms of solution quality. We propose to integrate min-cut placement with fixed-outline floor-planning to solve the more general placement problem, which includes cell placement, floorplanning, mixed-size placement and achieving routability. At every step of min-cut placement, either partitioning or wirelength-driven, fixed-outline floorplanning is invoked. If the latter fails, we undo an earlier partitioning decision, merge adjacent placement regions and re-floorplan the larger region to find a legal placement for the macros. Empirically, this framework improves the scalability and quality of results for traditional wirelength-driven floorplanning. It has been validated on recent designs with embedded memories and accounts for routability. Additionally, we propose that free-shape rectilinear floorplanning can be used with rough module-area estimates before synthesis.","PeriodicalId":255227,"journal":{"name":"IEEE/ACM International Conference on Computer Aided Design, 2004. ICCAD-2004.","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126954551","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A metal and via maskset programmable VLSI design methodology using PLAs","authors":"N. Jayakumar, S. Khatri","doi":"10.1109/ICCAD.2004.1382645","DOIUrl":"https://doi.org/10.1109/ICCAD.2004.1382645","url":null,"abstract":"In recent times there has been a substantial increase in the cost and complexity of fabricating a VLSI chip. The lithography masks themselves can cost between /spl epsi/ and /spl ges/. It is conjectured that due to these increasing costs, the number of ASIC starts in the last few years has declined. We address this problem by using an array of dynamic PLAs which require only metal and via mask customization in order to implement a new design. This would allow several similar-sized designs to share the same base set of masks (right up to the metal layers) and only have different metal and via masks. We have implemented our methodology for both combinational and sequential designs, and demonstrate that our approach strikes a reasonable compromise between ASIC and field programmable design methodologies in terms of placed-and-routed area and delay. Our method has a 2.89/spl times/ (3.58/spl times/) delay overhead and a 4.96/spl times/ (3.44/spl times/) area overhead compared to standard cells for combinational (sequential) designs.","PeriodicalId":255227,"journal":{"name":"IEEE/ACM International Conference on Computer Aided Design, 2004. ICCAD-2004.","volume":"109 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123650315","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Analytical modeling of crosstalk noise waveforms using Weibull function","authors":"Alireza Kasnavi, Joddy W. Wang, M. Shahram, Jindrich Zejda","doi":"10.1109/ICCAD.2004.1382561","DOIUrl":"https://doi.org/10.1109/ICCAD.2004.1382561","url":null,"abstract":"To analyze the failure of a CMOS circuit due to glitches induced by capacitive crosstalk, noise immunity curves (a.k.a. noise rejection curve) must be characterized. However, noise waveform models currently used for characterization such as ideal triangle and trapezoid can underestimate the propagated noise pulse by over 20% and result in missed violations. We provide an analytical solution to fit any given crosstalk noise waveform to a Weibull function, which can generate identical propagated glitch heights compared to SPICE, resulting in accurate noise immunity curves.","PeriodicalId":255227,"journal":{"name":"IEEE/ACM International Conference on Computer Aided Design, 2004. ICCAD-2004.","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114827191","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"The effects of energy management on reliability in real-time embedded systems","authors":"Dakai Zhu, R. Melhem, D. Mossé","doi":"10.1109/ICCAD.2004.1382539","DOIUrl":"https://doi.org/10.1109/ICCAD.2004.1382539","url":null,"abstract":"The slack time in real-time systems can be used by recovery schemes to increase system reliability as well as by frequency and voltage scaling techniques to save energy. Moreover, the rate of transient faults (i.e., soft errors caused, for example, by cosmic ray radiations) also depends on system operating frequency and supply voltage. Thus, there is an interesting trade-off between system reliability and energy consumption. This work first investigates the effects of frequency and voltage scaling on the fault rate and proposes two fault rate models based on previously published data. Then, the effects of energy management on reliability are studied. Our analysis results show that, energy management through frequency and voltage scaling could dramatically reduce system reliability, and ignoring the effects of energy management on the fault rate is too optimistic and may lead to unsatisfied system reliability.","PeriodicalId":255227,"journal":{"name":"IEEE/ACM International Conference on Computer Aided Design, 2004. ICCAD-2004.","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122021021","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Architectural-level synthesis of digital microfluidics-based biochips","authors":"Fei Su, K. Chakrabarty","doi":"10.1109/ICCAD.2004.1382576","DOIUrl":"https://doi.org/10.1109/ICCAD.2004.1382576","url":null,"abstract":"Microfluidics-based biochips offer a promising platform for massively parallel DNA analysis, automated drug discovery, and real-time biomolecular recognition. Current techniques for full-custom design of droplet-based \"digital\" biochips do not scale well for concurrent assays and for next-generation system-on-chip (SOC) designs that are expected to include fluidic components. We propose a system design methodology that attempts to apply classical architectural-level synthesis techniques to the design of digital microfluidics-based biochips. We first develop an optimal scheduling strategy based on integer linear programming. Since the scheduling problem is NP-complete, we also develop two heuristic techniques that scale well for large problem instances. A clinical diagnostic procedure, namely multiplexed in-vitro diagnostics on human physiological fluids, is used to evaluate the proposed method.","PeriodicalId":255227,"journal":{"name":"IEEE/ACM International Conference on Computer Aided Design, 2004. ICCAD-2004.","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125335092","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Multilevel expansion-based VLSI placement with blockages","authors":"Bo Hu, M. Marek-Sadowska","doi":"10.1109/ICCAD.2004.1382640","DOIUrl":"https://doi.org/10.1109/ICCAD.2004.1382640","url":null,"abstract":"The rapid growth of system-on-chip designs makes it a necessity for physical design tools to efficiently handle the coexistence of large intellectual property (IP) blocks and small standard cells in a single design. In this work, we present an efficient expansion-based placer to address standard-cell placement problem in the presence of blockages induced by pre-placed IP blocks. Expansion refers to the process during which cells are gradually distributed over a specified region. We implement expansion in a new placer by enhancing a quadratic placement technique based on fixed-point addition originally presented by B. Hu and M. Marek-Sadowska (2003), where fixed points were defined as dimensionless pseudo cells, and were deliberately introduced into the circuit to pull cells from one location to another. The new placer not only produces very competitive placement results over multiple sets of public-domain benchmarks with conventional rectangle-like chip boundary, but also efficiently handles the existence of blockages. Especially, we develop three expansion strategies and use them under different blockage settings.","PeriodicalId":255227,"journal":{"name":"IEEE/ACM International Conference on Computer Aided Design, 2004. ICCAD-2004.","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126366849","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Fast flip-chip power grid analysis via locality and grid shells","authors":"E. Chiprout","doi":"10.1109/ICCAD.2004.1382626","DOIUrl":"https://doi.org/10.1109/ICCAD.2004.1382626","url":null,"abstract":"Full-chip power grid analysis is time consuming. Several techniques have been proposed to tackle the problem but typically they deal with the power grid as a whole or partition at unnatural boundaries. Using a locality effect under flip-chip packaging, we propose a natural partitioning approach based on overlapping power grid \"shells\". The technique makes more efficient any previous simulation techniques that are polynomial in grid size. It is also parallelizable and therefore extremely fast. Using complete partitions gives no loss of accuracy compared to a full matrix solution, while lesser partitions are conservative for droop and current. Results on a recent Pentium/spl reg/ microprocessor design show excellent speed and accuracy.","PeriodicalId":255227,"journal":{"name":"IEEE/ACM International Conference on Computer Aided Design, 2004. ICCAD-2004.","volume":"228 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122706917","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Formal verification coverage: computing the coverage gap between temporal specifications","authors":"Sayantan Das, P. Basu, A. Banerjee, P. Dasgupta, P. Chakrabarti, C. Mohan, L. Fix, R. Armoni","doi":"10.1109/ICCAD.2004.1382571","DOIUrl":"https://doi.org/10.1109/ICCAD.2004.1382571","url":null,"abstract":"Existing methods for formal verification coverage compare a given specification with a given implementation, and evaluate the coverage gap in terms of quantitative metrics. We consider a new problem, namely to compare two formal temporal specifications and to find a set of additional temporal properties that close the coverage gap between the two specifications. In this paper we present: (1) the problem definition and motivation, (2) a methodology for computing the coverage gap between specifications, and (3) a methodology for representing the coverage gap as a collection of temporal properties that preserve the syntactic structure of the target specification.","PeriodicalId":255227,"journal":{"name":"IEEE/ACM International Conference on Computer Aided Design, 2004. ICCAD-2004.","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130075410","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Timing macro-modeling of IP blocks with crosstalk","authors":"Ruiming Chen, H. Zhou","doi":"10.1109/ICCAD.2004.1382563","DOIUrl":"https://doi.org/10.1109/ICCAD.2004.1382563","url":null,"abstract":"With the increase of design complexities and the decrease of minimal feature sizes, IP reuse is becoming a common practice while crosstalk is becoming a critical issue that must be considered. This work presents two macro-models for specifying the timing behaviors of combinational hard IP blocks with crosstalk effects. The gray-box model keeps a coupling graph and lists the conditions on relative input arrival time combinations for couplings not to take effect. The black-box model stores the output response windows for a basic set of relative input arrival time combinations, and computes the output arrival time for any given input arrival time combination through the union of some combinations in the basic set. Both macro-models are conservative, and can greatly reduce the pessimism existing in the conventional \"pin-to-pin\" model. This is the first work to deal with timing macro-modeling of combinational hard IP blocks with the consideration of crosstalk effects.","PeriodicalId":255227,"journal":{"name":"IEEE/ACM International Conference on Computer Aided Design, 2004. ICCAD-2004.","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128221452","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}