IEEE/ACM International Conference on Computer Aided Design, 2004. ICCAD-2004.最新文献_第8页

A general framework for probabilistic low-power design space exploration considering process variation 考虑工艺变化的概率性低功耗设计空间探索的一般框架

IEEE/ACM International Conference on Computer Aided Design, 2004. ICCAD-2004. Pub Date : 2004-11-07 DOI: 10.1109/ICCAD.2004.1382686

A. Srivastava, D. Sylvester

引用次数: 11

Physical design at 90nm and beyond [Tutorial 2] 90纳米及以上的物理设计[教程2]

IEEE/ACM International Conference on Computer Aided Design, 2004. ICCAD-2004. Pub Date : 2004-11-07 DOI: 10.1109/ICCAD.2004.1382524

A. Kahng, P. J. Osler

引用次数: 0

Physical placement driven by sequential timing analysis 由时序分析驱动的物理位置

IEEE/ACM International Conference on Computer Aided Design, 2004. ICCAD-2004. Pub Date : 2004-11-07 DOI: 10.1109/ICCAD.2004.1382605

A. Hurst, P. Chong, A. Kuehlmann

{"title":"Physical placement driven by sequential timing analysis","authors":"A. Hurst, P. Chong, A. Kuehlmann","doi":"10.1109/ICCAD.2004.1382605","DOIUrl":"https://doi.org/10.1109/ICCAD.2004.1382605","url":null,"abstract":"Traditional timing-driven placement considers only combinational delays and does not take into account the potential of subsequent sequential optimization steps. As a result, the potential of re-balancing path delays through post-placement applications of clock skew scheduling and in-place retiming cannot be fully realized. In this paper we describe a new placement algorithm that is based on a tight integration of sequential timing analysis in the inner loop of an analytic solver. Instead of minimizing the maximum path delay, our approach minimizes the maximum mean delay on any circuit loop, thus enabling the full optimization potential of clock skew scheduling and in-place retiming. We present two versions of the new algorithm: one approximates sequential criticality and weights wires accordingly (Cong and Lim, 2000), the other extends this with the inclusion of explicit wire-length constraints for loops that limit the final clock period. Our algorithms are implemented using a hybrid, GORDlAN-style sequence of analytical placement steps interleaved with cell partitioning (Kleinhans et al., 1988). Our experiments on a set of large industrial designs demonstrate that the presented placement algorithm can minimize the contribution of interconnection delays to the clock period on average by 23.5% compared to a solution based on combinational delays.","PeriodicalId":255227,"journal":{"name":"IEEE/ACM International Conference on Computer Aided Design, 2004. ICCAD-2004.","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116984023","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 28

Adaptive sampling and modeling of analog circuit performance parameters with pseudo-cubic splines 模拟电路性能参数的拟三次样条自适应采样与建模

IEEE/ACM International Conference on Computer Aided Design, 2004. ICCAD-2004. Pub Date : 2004-11-07 DOI: 10.1109/ICCAD.2004.1382709

Glenn Wolfe, Mengmeng Ding, R. Vemuri

引用次数: 19

Process and environmental variation impacts on ASIC timing 工艺和环境变化对ASIC时序的影响

IEEE/ACM International Conference on Computer Aided Design, 2004. ICCAD-2004. Pub Date : 2004-11-07 DOI: 10.1109/ICCAD.2004.1382597

P. Zuchowski, P. Habitz, J. Hayes, J. Oppold

引用次数: 112

Soft self-synchronising codes for self-calibrating communication 用于自校准通信的软自同步代码

IEEE/ACM International Conference on Computer Aided Design, 2004. ICCAD-2004. Pub Date : 2004-11-07 DOI: 10.1109/ICCAD.2004.1382617

F. Worm, P. Ienne, Patrick Thiran

引用次数: 9

Simultaneous escape routing and layer assignment for dense PCBs 密集pcb的同时逃逸路由和层分配

IEEE/ACM International Conference on Computer Aided Design, 2004. ICCAD-2004. Pub Date : 2004-11-07 DOI: 10.1109/ICCAD.2004.1382689

Muhammet Mustafa Ozdal, Martin D. F. Wong

{"title":"Simultaneous escape routing and layer assignment for dense PCBs","authors":"Muhammet Mustafa Ozdal, Martin D. F. Wong","doi":"10.1109/ICCAD.2004.1382689","DOIUrl":"https://doi.org/10.1109/ICCAD.2004.1382689","url":null,"abstract":"As die sizes are shrinking, and circuit complexities are increasing, the PCB routing problem becomes more and more challenging. Traditional routing algorithms can not handle these challenges effectively, and many high-end designs in the industry require manual routing efforts. In this paper, we propose a problem decomposition that distinguishes routing within dense components from routing in the intermediate area. In particular, we propose an effective methodology to find the escape routing solution for multiple components simultaneously such that the number of crossings in the intermediate area is minimized. For this, we model the problem as a longest path with forbidden pairs (LPFP) problem, and propose two algorithms for it. The first is an exact polynomial-time algorithm that is guaranteed to find the maximal planar routing solution on one layer. The second is a randomized algorithm that has good scalability characteristics for large circuits. Then we use these algorithms to assign the maximal subset of planar nets to each layer, and then distribute the remaining nets at the end. We demonstrate the effectiveness of these algorithms through experiments on industrial circuits.","PeriodicalId":255227,"journal":{"name":"IEEE/ACM International Conference on Computer Aided Design, 2004. ICCAD-2004.","volume":"90 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116010940","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 41

Design/process learning from electrical test 从电气测试中学习设计/流程

IEEE/ACM International Conference on Computer Aided Design, 2004. ICCAD-2004. Pub Date : 2004-11-07 DOI: 10.1109/ICCAD.2004.1382673

B. Koenemann

引用次数: 8

SPIN-TEST: automatic test pattern generation for speed-independent circuits SPIN-TEST:自动生成速度无关电路的测试图

IEEE/ACM International Conference on Computer Aided Design, 2004. ICCAD-2004. Pub Date : 2004-11-07 DOI: 10.1109/ICCAD.2004.1382703

Feng Shi, Y. Makris

引用次数: 10

Techniques for improving the accuracy of geometric-programming based analog circuit design optimization 提高基于几何编程的模拟电路设计优化精度的技术

IEEE/ACM International Conference on Computer Aided Design, 2004. ICCAD-2004. Pub Date : 2004-11-07 DOI: 10.1109/ICCAD.2004.1382695

Jintae Kim, Jaeseo Lee, L. Vandenberghe

引用次数: 61