IEEE/ACM International Conference on Computer Aided Design, 2004. ICCAD-2004.最新文献_第2页

True crosstalk aware incremental placement with noise map 真正的串音感知增量放置与噪声图

IEEE/ACM International Conference on Computer Aided Design, 2004. ICCAD-2004. Pub Date : 2004-11-07 DOI: 10.1109/ICCAD.2004.1382608

Haoxing Ren, D. Pan, P. Villarrubia

{"title":"True crosstalk aware incremental placement with noise map","authors":"Haoxing Ren, D. Pan, P. Villarrubia","doi":"10.1109/ICCAD.2004.1382608","DOIUrl":"https://doi.org/10.1109/ICCAD.2004.1382608","url":null,"abstract":"Crosstalk noise has become an important issue as technology scales down for timing and signal integrity closure. Existing works to fix crosstalk noise are mostly done at the routing or post routing stage, which may be too late. Since placement determines the overall routing congestion, which correlates with the coupling capacitance, which in turn correlates with the crosstalk noise, placement shall be a good level to do early noise mitigation. The only existing work for the crosstalk aware placement (to our best knowledge) is by Lou and Chen (2004), which uses the coupling capacitance map to guide placement. However, crosstalk is determined not only by the coupling capacitance, but also by many other factors, such as the driver resistance of the victim net and the coupling location (near source vs near sink coupling) (Cong et al., 2001). We introduce a concept of noise map which takes those factors into account. Guided by this accurate noise map explicitly, we propose an incremental placement technique to mitigate noise without disturbing the global placement order. Our incremental placement has two key steps, namely noise aware cell inflation and local refinement. Experimental results on industrial circuits show that our approach is able to reduce the number of top noise nets by 25% and improve the timing (300ps on the worst slack), with no wire length penalty or CPU overhead. Our incremental approach is also able to maintain the placement stability.","PeriodicalId":255227,"journal":{"name":"IEEE/ACM International Conference on Computer Aided Design, 2004. ICCAD-2004.","volume":"324 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124299581","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 24

Modeling unbuffered latches for timing analysis 建模无缓冲锁存器进行时序分析

IEEE/ACM International Conference on Computer Aided Design, 2004. ICCAD-2004. Pub Date : 2004-11-07 DOI: 10.1109/ICCAD.2004.1382582

C. Amin, F. Dartu, Y. Ismail

引用次数: 1

On interactions between routing and detailed placement 论路线与详细布置的相互作用

IEEE/ACM International Conference on Computer Aided Design, 2004. ICCAD-2004. Pub Date : 2004-11-07 DOI: 10.1109/ICCAD.2004.1382606

Devang Jariwala, J. Lillis

引用次数: 16

Routability-driven placement and white space allocation 可达性驱动的布局和空白空间分配

IEEE/ACM International Conference on Computer Aided Design, 2004. ICCAD-2004. Pub Date : 2004-11-07 DOI: 10.1109/TCAD.2006.884575

Chen Li, M. Xie, Cheng-Kok Koh, J. Cong, P. Madden

引用次数: 121

Backend CAD flows for "restrictive design rules" “限制性设计规则”的后端CAD流程

IEEE/ACM International Conference on Computer Aided Design, 2004. ICCAD-2004. Pub Date : 2004-11-07 DOI: 10.1109/ICCAD.2004.1382674

M. Lavin, Fook-Luen Heng, G. Northrop

引用次数: 57

Automated oscillator macromodelling techniques for capturing amplitude variations and injection locking 用于捕获振幅变化和注入锁定的自动振荡器宏观建模技术

IEEE/ACM International Conference on Computer Aided Design, 2004. ICCAD-2004. Pub Date : 2004-11-07 DOI: 10.1109/ICCAD.2004.1382663

X. Lai, J. Roychowdhury

引用次数: 40

An efficient method for improving the quality of per-test fault diagnosis 一种提高单测故障诊断质量的有效方法

IEEE/ACM International Conference on Computer Aided Design, 2004. ICCAD-2004. Pub Date : 2004-11-07 DOI: 10.1109/ICCAD.2004.1382655

Chunsheng Liu

引用次数: 2

How to bridge the abstraction gap in system level modeling and design 如何在系统级建模和设计中弥合抽象的鸿沟

IEEE/ACM International Conference on Computer Aided Design, 2004. ICCAD-2004. Pub Date : 2004-11-07 DOI: 10.1109/ICCAD.2004.1382705

A. Bernstein, M. Burton, F. Ghenassia

{"title":"How to bridge the abstraction gap in system level modeling and design","authors":"A. Bernstein, M. Burton, F. Ghenassia","doi":"10.1109/ICCAD.2004.1382705","DOIUrl":"https://doi.org/10.1109/ICCAD.2004.1382705","url":null,"abstract":"As more and more processors and subsystems are integrated in a single system, the verification bottleneck is driving designers away from RTL and RTL-like strategies for verification and design to higher abstraction levels. Increasing system complexity at the other hand requires much faster simulation and analysis tools. This is leading to new standards and tools around transaction level modeling. Languages such as SystemC and SystemVerilog are rich in behavioral and structural constructs which enable modeling designs at different levels of abstraction without imposing a top-down or bottom-up design flow. In fact, most design flows are iterative and modules at different levels of abstractions have to be considered. A more abstract model is very useful to increase simulation speed and to improve formal verification. SystemC and SystemVerilog stress the importance of verification support for complex SOCs including improvement for hardware verification as well as for the verification of hardware dependent software. In todays design flows the software development can often only start after the hardware is available. This causes unacceptable delays for the software development. The idea of transaction level modeling (TLM) is to provide in an early phase of the hardware development transaction level models of the hardware. Based on these TLMs a fast enough simulation environment is the basis for the development of hardware and hardware dependent software. The presumption is to run these transaction level models at several tens or some hundreds of thousand transactions per second which should be fast enough for system level modeling and verification.","PeriodicalId":255227,"journal":{"name":"IEEE/ACM International Conference on Computer Aided Design, 2004. ICCAD-2004.","volume":"258 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114547850","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 13

Analyzing software influences on substrate noise: an ADC perspective 分析软件对基板噪声的影响:ADC视角

IEEE/ACM International Conference on Computer Aided Design, 2004. ICCAD-2004. Pub Date : 2004-11-07 DOI: 10.1109/ICCAD.2004.1382707

F. Ghenassia, N. Vijaykrishnan, M. J. Irwin

引用次数: 0

DAOmap: a depth-optimal area optimization mapping algorithm for FPGA designs DAOmap:用于FPGA设计的深度最优区域优化映射算法

IEEE/ACM International Conference on Computer Aided Design, 2004. ICCAD-2004. Pub Date : 2004-11-07 DOI: 10.1109/ICCAD.2004.1382677

Deming Chen, J. Cong

{"title":"DAOmap: a depth-optimal area optimization mapping algorithm for FPGA designs","authors":"Deming Chen, J. Cong","doi":"10.1109/ICCAD.2004.1382677","DOIUrl":"https://doi.org/10.1109/ICCAD.2004.1382677","url":null,"abstract":"In This work we study the technology mapping problem for FPGA architectures to minimize chip area, or the total number of lookup tables (LUTs) of the mapped design, under the chip performance constraint. This is a well-studied topic and a very difficult task (NP-hard). The contributions of This work are as follows: (i) we consider the potential node duplications during the cut enumeration/generation procedure so the mapping costs encoded in the cuts drive the area-optimization objective more effectively; (ii) after the timing constraint is determined, we will relax the non-critical paths by searching the solution space considering both local and global optimality information to minimize mapping area; (iii) an iterative cut selection procedure is carried out that further explores and perturbs the solution space to improve solution quality. We guarantee optimal mapping depth under the unit delay model. Experimental results show that our mapping algorithm, named DAOmap, produces significant quality and runtime improvements. Compared to the state-of-the-art depth-optimal, area minimization mapping algorithm CutMap (Cong and Hwan, 1995), DAOmap is 16.02% better on area and runs 24.2X faster on average when both algorithms are mapping to FPGAs using LUTs of five inputs. LUTs of other inputs are also used for comparisons.","PeriodicalId":255227,"journal":{"name":"IEEE/ACM International Conference on Computer Aided Design, 2004. ICCAD-2004.","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116494015","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 158