IEEE/ACM International Conference on Computer Aided Design, 2004. ICCAD-2004.最新文献_第4页

Dynamic range estimation for nonlinear systems 非线性系统的动态范围估计

IEEE/ACM International Conference on Computer Aided Design, 2004. ICCAD-2004. Pub Date : 2004-11-07 DOI: 10.1109/ICCAD.2004.1382658

Bin Wu, Jianwen Zhu, F. Najm

引用次数: 21

Application-specific buffer space allocation for networks-on-chip router design 片上网络路由器设计中特定于应用程序的缓冲空间分配

IEEE/ACM International Conference on Computer Aided Design, 2004. ICCAD-2004. Pub Date : 2004-11-07 DOI: 10.1109/ICCAD.2004.1382601

Jingcao Hu, R. Marculescu

引用次数: 176

Banked scratch-pad memory management for reducing leakage energy consumption 银行刮刮板存储器管理，减少泄漏能源消耗

IEEE/ACM International Conference on Computer Aided Design, 2004. ICCAD-2004. Pub Date : 2004-11-07 DOI: 10.1109/ICCAD.2004.1382555

M. Kandemir, M. J. Irwin, Guilin Chen, I. Kolcu

引用次数: 33

Engineering details of a stable force-directed placer 稳定力导向砂矿的工程细节

IEEE/ACM International Conference on Computer Aided Design, 2004. ICCAD-2004. Pub Date : 2004-11-07 DOI: 10.1109/ICCAD.2004.1382642

Kristofer Vorwerk, A. Kennings, A. Vannelli

引用次数: 58

Diagnosis of small-signal parameters for broadband amplifiers through S-parameter measurements and sensitivity-guided evolutionary search 基于s参数测量和灵敏度导向进化搜索的宽带放大器小信号参数诊断

IEEE/ACM International Conference on Computer Aided Design, 2004. ICCAD-2004. Pub Date : 2004-11-07 DOI: 10.1109/ICCAD.2004.1382654

Fang Liu, S. Ozev, M. Brooke

引用次数: 3

Dynamic transition relation simplification for bounded property checking 有界属性检查的动态转换关系简化

IEEE/ACM International Conference on Computer Aided Design, 2004. ICCAD-2004. Pub Date : 2004-11-07 DOI: 10.1109/ICCAD.2004.1382542

A. Kuehlmann

{"title":"Dynamic transition relation simplification for bounded property checking","authors":"A. Kuehlmann","doi":"10.1109/ICCAD.2004.1382542","DOIUrl":"https://doi.org/10.1109/ICCAD.2004.1382542","url":null,"abstract":"Bounded model checking (BMC) is an incomplete property checking method that is based on a finite unfolding of the transition relation to disprove the correctness of a set of properties or to prove them for a limited execution length from the initial states. Current BMC techniques repeatedly concatenate the original transition relation to unfold the circuit with increasing depths. In this paper we present a method that is based on a dual unfolding scheme. The first unfolding is non-initialized and progressively simplifies concatenated frames of the transition relation. The tail of the simplified frames is then applied in the second unfolding, which starts from the initial state and checks the properties. We use a circuit graph representation for all functions and perform simplification by merging vertices that are functionally equivalent under given input constraints. In the noninitialized unfolding, previous time frames progressively tighten these constraints thus leading to an asymptotic simplification of the transition relation. As a side benefit, our method can find inductive invariants constructively by detecting when vertices are functionally equivalent across time frames. This information is then used to further simplify the transition relation and, in some cases, prove unbounded correctness of properties. Our experiments using industrial property checking problems demonstrate that the presented method significantly improves the efficiency of BMC.","PeriodicalId":255227,"journal":{"name":"IEEE/ACM International Conference on Computer Aided Design, 2004. ICCAD-2004.","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114829321","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 112

SILENT: serialized low energy transmission coding for on-chip interconnection networks SILENT:用于片上互连网络的串行低能量传输编码

IEEE/ACM International Conference on Computer Aided Design, 2004. ICCAD-2004. Pub Date : 2004-11-07 DOI: 10.1109/ICCAD.2004.1382618

Kangmin Lee, Se-Joong Lee, H. Yoo

引用次数: 95

A provably good algorithm for high performance bus routing 一种可证明的高性能总线路由算法

IEEE/ACM International Conference on Computer Aided Design, 2004. ICCAD-2004. Pub Date : 2004-11-07 DOI: 10.1109/ICCAD.2004.1382690

Muhammet Mustafa Ozdal, Martin D. F. Wong

引用次数: 15

SAPOR: second-order Arnoldi method for passive order reduction of RCS circuits RCS电路无源降阶的二阶Arnoldi法

IEEE/ACM International Conference on Computer Aided Design, 2004. ICCAD-2004. Pub Date : 2004-11-07 DOI: 10.1109/ICCAD.2004.1382546

Yangfeng Su, Jian Wang, Xuan Zeng, Z. Bai, C. Chiang, Dian Zhou

引用次数: 79

DAG-aware circuit compression for formal verification 形式验证的dag感知电路压缩

IEEE/ACM International Conference on Computer Aided Design, 2004. ICCAD-2004. Pub Date : 2004-11-07 DOI: 10.1109/ICCAD.2004.1382541

Per Bjesse, Arne Borälv

{"title":"DAG-aware circuit compression for formal verification","authors":"Per Bjesse, Arne Borälv","doi":"10.1109/ICCAD.2004.1382541","DOIUrl":"https://doi.org/10.1109/ICCAD.2004.1382541","url":null,"abstract":"The choice of representation for circuits and Boolean formulae in a formal verification tool is important for two reasons. First of all, representation compactness is necessary in order to keep the memory consumption low. This is witnessed by the importance of maximum processable design size for equivalence checkers. Second, many formal verification algorithms are sensitive to redundancies in the design that is processed. To address these concerns, three different auto-compressing representations for Boolean circuit networks and formulas have been suggested in the literature. We attempt to find a blend of features from these alternatives that allows us to remove as much redundancy as possible while not sacrificing runtime. By studying how the network representation size varies when we change parameters, we show that the use of only one operator node is suboptimal, and demonstrate that the most powerful of the proposed reduction rules, two-level minimization, actually can be harmful. We correct the bad behavior of two-level optimization by devising a simple linear simplification algorithm that can remove tens of thousands of nodes on examples where all obvious redundancies already have been removed. The combination of our compactor with the simplest representation outperforms all of the alternatives we have studied, with a theoretical runtime bound that is at least as good as the three studied representations.","PeriodicalId":255227,"journal":{"name":"IEEE/ACM International Conference on Computer Aided Design, 2004. ICCAD-2004.","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130374778","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 101